From patchwork Tue Jan 25 13:12:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 536572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACC8CC433F5 for ; Tue, 25 Jan 2022 13:15:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1575870AbiAYNPE (ORCPT ); Tue, 25 Jan 2022 08:15:04 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:40810 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1575809AbiAYNMg (ORCPT ); Tue, 25 Jan 2022 08:12:36 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 20PDCZGc111935; Tue, 25 Jan 2022 07:12:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643116355; bh=d76i5L4O9W7burlhFss6iuuswI1RV/QfLL2FiWDnHME=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jAQu0yzWp7Bo5FqErnZqBngND/PgdVDnQXTVJBMKZPavTVrDU6rkeIsoLaBXLUyMr SweQQ+7xOo2usfSLlM2lg5UDEm0mXvbh/l5leGSOWg8D7VxfPqmoJ6n63k0xI4K6nP TmzDEhz+q2y4Nt9g7vsaxJGmIE3US/neI/TZbrdI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 20PDCYMd064929 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 25 Jan 2022 07:12:35 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 25 Jan 2022 07:12:34 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 25 Jan 2022 07:12:34 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20PDCPWF008001; Tue, 25 Jan 2022 07:12:32 -0600 From: Aswath Govindraju CC: , , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Kishon Vijay Abraham I , Aswath Govindraju Subject: [PATCH 2/2] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Tue, 25 Jan 2022 18:42:25 +0530 Message-ID: <20220125131225.871-3-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220125131225.871-1-a-govindraju@ti.com> References: <20220125131225.871-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Signed-off-by: Aswath Govindraju --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index cb99a97af426..793ee77838f4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -428,6 +428,20 @@ }; }; +&pcie1_rc { + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; + &mcu_mcan0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>;