From patchwork Thu Mar 24 15:56:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 553945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93105C433EF for ; Thu, 24 Mar 2022 15:58:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351619AbiCXP7g (ORCPT ); Thu, 24 Mar 2022 11:59:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351502AbiCXP71 (ORCPT ); Thu, 24 Mar 2022 11:59:27 -0400 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D262FADD67; Thu, 24 Mar 2022 08:57:40 -0700 (PDT) Received: from localhost.localdomain ([81.221.85.15]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MCJn4-1nPCdq18T4-009PGS; Thu, 24 Mar 2022 16:57:16 +0100 From: Marcel Ziswiler To: linux-arm-kernel@lists.infradead.org Cc: Marcel Ziswiler , Andrejs Cainikovs , Arnd Bergmann , Fabio Estevam , Frank Rowand , Krzysztof Kozlowski , NXP Linux Team , Olof Johansson , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 06/10] arm64: dts: imx8mm-verdin: update iomux configuration Date: Thu, 24 Mar 2022 16:56:45 +0100 Message-Id: <20220324155649.285924-7-marcel@ziswiler.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220324155649.285924-1-marcel@ziswiler.com> References: <20220324155649.285924-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:xEc+FKGNDUKDBq+QNNSuhc9gvTAISzFiRaE3RF25NY+RHc2m7xd SltXB36SgxMgfr9L4z9vu5/iUe7OFf94CK8anPV3nwLlGzKsTYKLXntzVtSGnm+cd8Auwrh BTjEaADA373LzSQgB6FjI1Hi8786s7nNE2KK1d7Ahyiq4rWF/Tq/o+0ldn165Rn8wtP0ts0 2MVMiSzkq4OKGQ+RZTwrw== X-UI-Out-Filterresults: notjunk:1;V03:K0:hbLJtEPG2ts=:hDnRezwQYSAEnQJXU+MbqQ mYNvBkHfeurKotkhErxJNB6Z6PBrMcIr6NUzQIWYxsTRESZMDwZxwwTRc8cjIdWSzt3Wx1CyS dlmbk7VBJlafBeGUer6Ncv17+A3D40buRZF2d4vW7FoSUqIXMXp9hzfKmtkuEOI1YY4pCbMMo SfBXqPCkhijYc3UoxqskPefroZ4aF6LJIj15d8hDnWTp0AydZ7seQWCjW3VxVERQUDg2XhiaU htfGHkQmIrr6gCuhiosr+wkpLk95SAagQV5hVsvYqkkdSFlJSuraKZXVmHdJJyqAPRsUcC42V hu+i45+1CKdyMrqNgLDvRcolE/BDFmurTjE0M1rfobiywOAyuZ7BXJEz/Rt9WgtC85c58WG9c m26i6DhWI71rYmJCnDemSoscrYORxWjqjqPttFLXeLpCpNBIBOfFii397TjfbYki+Xu82sPTh eSvqq74Gctwh05XWmDBb/DdHy0LVH915w9BBJvpMsaZZ4tLhdPryt5QjzNBBdW+VGpqCD1Lx3 deTQWoBm75Qk6RF1Nuf2S9EyJ7fASq9yP5BRpiWoP1JFaCnaOZ2sdw+3uzo3xEQpaVTbT6F4x pRO8+gFjYI1l3l6lbp6kt77HWhC8Vai1jQBfHpz92MsF+wBb8gLtL5gQDoRR39FFcTaE91tn9 8A1O3kCKDnfbM1kYtZjewJ/eff2vOwYZ3xdE2syhhuwhMCOv8TSh9LNtNhxOjgdTXYYDR32j5 xCsWxDKUl/xu7qaU Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Marcel Ziswiler Update IOMUX configuration as required by the hardware design team. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 304 +++++++++--------- 1 file changed, 152 insertions(+), 152 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 4542c99ce906..7976d055f17b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -781,34 +781,34 @@ &iomuxc { pinctrl_can1_int: can1intgrp { fsl,pins = - ; /* CAN_1_SPI_INT#_1.8V */ + ; /* CAN_1_SPI_INT#_1.8V */ }; pinctrl_can2_int: can2intgrp { fsl,pins = - ; /* CAN_2_SPI_INT#_1.8V */ + ; /* CAN_2_SPI_INT#_1.8V, unused */ }; pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = - ; /* SODIMM 256 */ + ; /* SODIMM 256 */ }; pinctrl_ecspi2: ecspi2grp { fsl,pins = - , /* SODIMM 196 */ - , /* SODIMM 200 */ - , /* SODIMM 198 */ - ; /* SODIMM 202 */ + , /* SODIMM 196 */ + , /* SODIMM 200 */ + , /* SODIMM 198 */ + ; /* SODIMM 202 */ }; pinctrl_ecspi3: ecspi3grp { fsl,pins = - , /* CAN_SPI_SCK_1.8V */ - , /* CAN_SPI_MOSI_1.8V */ - , /* CAN_SPI_MISO_1.8V */ - , /* CAN_1_SPI_CS_1.8V# */ - ; /* CAN_2_SPI_CS#_1.8V */ + , /* CAN_SPI_SCK_1.8V */ + , /* CAN_SPI_MOSI_1.8V */ + , /* CAN_SPI_MISO_1.8V */ + , /* CAN_1_SPI_CS_1.8V# */ + ; /* CAN_2_SPI_CS#_1.8V */ }; pinctrl_fec1: fec1grp { @@ -827,7 +827,7 @@ pinctrl_fec1: fec1grp { , , , - ; + ; }; pinctrl_fec1_sleep: fec1-sleepgrp { @@ -846,170 +846,170 @@ pinctrl_fec1_sleep: fec1-sleepgrp { , , , - ; + ; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = - , /* SODIMM 52 */ - , /* SODIMM 54 */ - , /* SODIMM 64 */ - , /* SODIMM 66 */ - , /* SODIMM 56 */ - , /* SODIMM 58 */ - , /* SODIMM 60 */ - ; /* SODIMM 62 */ + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + ; /* SODIMM 62 */ }; pinctrl_gpio1: gpio1grp { fsl,pins = - ; /* SODIMM 206 */ + ; /* SODIMM 206 */ }; pinctrl_gpio2: gpio2grp { fsl,pins = - ; /* SODIMM 208 */ + ; /* SODIMM 208 */ }; pinctrl_gpio3: gpio3grp { fsl,pins = - ; /* SODIMM 210 */ + ; /* SODIMM 210 */ }; pinctrl_gpio4: gpio4grp { fsl,pins = - ; /* SODIMM 212 */ + ; /* SODIMM 212 */ }; pinctrl_gpio5: gpio5grp { fsl,pins = - ; /* SODIMM 216 */ + ; /* SODIMM 216 */ }; pinctrl_gpio6: gpio6grp { fsl,pins = - ; /* SODIMM 218 */ + ; /* SODIMM 218 */ }; pinctrl_gpio7: gpio7grp { fsl,pins = - ; /* SODIMM 220 */ + ; /* SODIMM 220 */ }; pinctrl_gpio8: gpio8grp { fsl,pins = - ; /* SODIMM 222 */ + ; /* SODIMM 222 */ }; /* Verdin GPIO_9_DSI (pulled-up as active-low) */ pinctrl_gpio_9_dsi: gpio9dsigrp { fsl,pins = - ; /* SODIMM 17 */ + ; /* SODIMM 17 */ }; - /* Verdin GPIO_10_DSI */ + /* Verdin GPIO_10_DSI (pulled-up as active-low) */ pinctrl_gpio_10_dsi: gpio10dsigrp { fsl,pins = - ; /* SODIMM 21 */ + ; /* SODIMM 21 */ }; pinctrl_gpio_hog1: gpiohog1grp { fsl,pins = - , /* SODIMM 88 */ - , /* SODIMM 90 */ - , /* SODIMM 92 */ - , /* SODIMM 94 */ - , /* SODIMM 96 */ - , /* SODIMM 100 */ - , /* SODIMM 102 */ - , /* SODIMM 104 */ - , /* SODIMM 106 */ - , /* SODIMM 108 */ - , /* SODIMM 112 */ - , /* SODIMM 114 */ - , /* SODIMM 116 */ - , /* SODIMM 118 */ - ; /* SODIMM 120 */ + , /* SODIMM 88 */ + , /* SODIMM 90 */ + , /* SODIMM 92 */ + , /* SODIMM 94 */ + , /* SODIMM 96 */ + , /* SODIMM 100 */ + , /* SODIMM 102 */ + , /* SODIMM 104 */ + , /* SODIMM 106 */ + , /* SODIMM 108 */ + , /* SODIMM 112 */ + , /* SODIMM 114 */ + , /* SODIMM 116 */ + , /* SODIMM 118 */ + ; /* SODIMM 120 */ }; pinctrl_gpio_hog2: gpiohog2grp { fsl,pins = - ; /* SODIMM 91 */ + ; /* SODIMM 91 */ }; pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = - , /* SODIMM 157 */ - ; /* SODIMM 187 */ + , /* SODIMM 157 */ + ; /* SODIMM 187 */ }; pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = - ; /* SODIMM 252 */ + ; /* SODIMM 252 */ }; /* On-module I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = - , /* PMIC_I2C_SCL */ - ; /* PMIC_I2C_SDA */ + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = - , /* PMIC_I2C_SCL */ - ; /* PMIC_I2C_SDA */ + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ }; /* Verdin I2C_4_CSI */ pinctrl_i2c2: i2c2grp { fsl,pins = - , /* SODIMM 55 */ - ; /* SODIMM 53 */ + , /* SODIMM 55 */ + ; /* SODIMM 53 */ }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = - , /* SODIMM 55 */ - ; /* SODIMM 53 */ + , /* SODIMM 55 */ + ; /* SODIMM 53 */ }; /* Verdin I2C_2_DSI */ pinctrl_i2c3: i2c3grp { fsl,pins = - , /* SODIMM 95 */ - ; /* SODIMM 93 */ + , /* SODIMM 95 */ + ; /* SODIMM 93 */ }; pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = - , /* SODIMM 95 */ - ; /* SODIMM 93 */ + , /* SODIMM 95 */ + ; /* SODIMM 93 */ }; /* Verdin I2C_1 */ pinctrl_i2c4: i2c4grp { fsl,pins = - , /* SODIMM 14 */ - ; /* SODIMM 12 */ + , /* SODIMM 14 */ + ; /* SODIMM 12 */ }; pinctrl_i2c4_gpio: i2c4gpiogrp { fsl,pins = - , /* SODIMM 14 */ - ; /* SODIMM 12 */ + , /* SODIMM 14 */ + ; /* SODIMM 12 */ }; /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = - ; /* SODIMM 42 */ + ; /* SODIMM 42 */ }; /* Verdin I2S_2_D_OUT shared with SAI5 */ pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { fsl,pins = - ; /* SODIMM 46 */ + ; /* SODIMM 46 */ }; pinctrl_pcie0: pcie0grp { @@ -1021,7 +1021,7 @@ pinctrl_pcie0: pcie0grp { pinctrl_pmic: pmicirqgrp { fsl,pins = - ; /* PMIC_INT# */ + ; /* PMIC_INT# */ }; /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ @@ -1043,82 +1043,82 @@ pinctrl_pwm_3: pwm3grp { /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { fsl,pins = - ; /* SODIMM 19 */ + ; /* SODIMM 19 */ }; pinctrl_reg_eth: regethgrp { fsl,pins = - ; /* PMIC_EN_ETH */ + ; /* PMIC_EN_ETH */ }; pinctrl_reg_usb1_en: regusb1engrp { fsl,pins = - ; /* SODIMM 155 */ + ; /* SODIMM 155 */ }; pinctrl_reg_usb2_en: regusb2engrp { fsl,pins = - ; /* SODIMM 185 */ + ; /* SODIMM 185 */ }; pinctrl_sai2: sai2grp { fsl,pins = - , /* SODIMM 32 */ - , /* SODIMM 30 */ - , /* SODIMM 38 */ - , /* SODIMM 36 */ - ; /* SODIMM 34 */ + , /* SODIMM 32 */ + , /* SODIMM 30 */ + , /* SODIMM 38 */ + , /* SODIMM 36 */ + ; /* SODIMM 34 */ }; pinctrl_sai5: sai5grp { fsl,pins = - , /* SODIMM 48 */ - , /* SODIMM 44 */ - , /* SODIMM 42 */ - ; /* SODIMM 46 */ + , /* SODIMM 48 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 46 */ }; /* control signal for optional ATTPM20P or SE050 */ pinctrl_pmic_tpm_ena: pmictpmenagrp { fsl,pins = - ; /* PMIC_TPM_ENA */ + ; /* PMIC_TPM_ENA */ }; pinctrl_tsp: tspgrp { fsl,pins = - , /* SODIMM 148 */ - , /* SODIMM 152 */ - , /* SODIMM 154 */ - , /* SODIMM 174 */ - ; /* SODIMM 150 */ + , /* SODIMM 148 */ + , /* SODIMM 152 */ + , /* SODIMM 154 */ + , /* SODIMM 174 */ + ; /* SODIMM 150 */ }; pinctrl_uart1: uart1grp { fsl,pins = - , /* SODIMM 149 */ - ; /* SODIMM 147 */ + , /* SODIMM 149 */ + ; /* SODIMM 147 */ }; pinctrl_uart2: uart2grp { fsl,pins = - , /* SODIMM 129 */ - , /* SODIMM 131 */ - , /* SODIMM 133 */ - ; /* SODIMM 135 */ + , /* SODIMM 129 */ + , /* SODIMM 131 */ + , /* SODIMM 133 */ + ; /* SODIMM 135 */ }; pinctrl_uart3: uart3grp { fsl,pins = - , /* SODIMM 137 */ - , /* SODIMM 139 */ - , /* SODIMM 141 */ - ; /* SODIMM 143 */ + , /* SODIMM 137 */ + , /* SODIMM 139 */ + , /* SODIMM 141 */ + ; /* SODIMM 143 */ }; pinctrl_uart4: uart4grp { fsl,pins = - , /* SODIMM 151 */ - ; /* SODIMM 153 */ + , /* SODIMM 151 */ + ; /* SODIMM 153 */ }; pinctrl_usdhc1: usdhc1grp { @@ -1171,45 +1171,45 @@ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = - ; /* SODIMM 84 */ + ; /* SODIMM 84 */ }; pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = - ; /* SODIMM 76 */ + ; /* SODIMM 76 */ }; pinctrl_usdhc2: usdhc2grp { fsl,pins = - , /* SODIMM 78 */ - , /* SODIMM 74 */ - , /* SODIMM 80 */ - , /* SODIMM 82 */ - , /* SODIMM 70 */ - , /* SODIMM 72 */ - ; + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + , /* SODIMM 72 */ + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; }; /* @@ -1218,56 +1218,56 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { */ pinctrl_usdhc3: usdhc3grp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_wdog: wdoggrp { fsl,pins = - ; /* PMIC_WDI */ + ; /* PMIC_WDI */ }; pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = - , /* WIFI_WKUP_BT */ - , /* WIFI_W_WKUP_HOST */ - ; /* WIFI_WKUP_WLAN */ + , /* WIFI_WKUP_BT */ + , /* WIFI_W_WKUP_HOST */ + ; /* WIFI_WKUP_WLAN */ }; pinctrl_wifi_i2s: bti2sgrp { fsl,pins = - , /* WIFI_TX_BCLK */ - , /* WIFI_TX_DATA0 */ - , /* WIFI_TX_SYNC */ - ; /* WIFI_RX_DATA0 */ + , /* WIFI_TX_BCLK */ + , /* WIFI_TX_DATA0 */ + , /* WIFI_TX_SYNC */ + ; /* WIFI_RX_DATA0 */ }; pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = - ; /* PMIC_EN_WIFI */ + ; /* PMIC_EN_WIFI */ }; };