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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id j3-20020adfd203000000b0020616cddfd5sm13901357wrh.7.2022.04.09.09.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 09:46:02 -0700 (PDT) From: Bryan O'Donoghue To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com, jgrahsl@snap.com, bryan.odonoghue@linaro.org Subject: [PATCH 4/4] arm64: dts: qcom: sm8250: camss: Add CCI definitions Date: Sat, 9 Apr 2022 17:45:56 +0100 Message-Id: <20220409164556.2832782-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> References: <20220409164556.2832782-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org sm8250 has two CCI busses with two I2C busses apiece. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 82 ++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 91ed079edbf7..98e96527702b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,88 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac4f000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4f000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac50000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac50000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci2_default &cci3_default>; + pinctrl-1 = <&cci2_sleep &cci3_sleep>; + + status = "disabled"; + + cci_i2c2: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c3: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@ac6a000 { compatible = "qcom,sm8250-camss"; status = "disabled";