From patchwork Mon May 2 22:41:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 568812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D2D5C41535 for ; Mon, 2 May 2022 22:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354179AbiEBWpK (ORCPT ); Mon, 2 May 2022 18:45:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236362AbiEBWpI (ORCPT ); Mon, 2 May 2022 18:45:08 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 457D4E096; Mon, 2 May 2022 15:41:38 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 60FCC22253; Tue, 3 May 2022 00:41:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1651531296; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0zWa7FnAehsT5VQr7sLCyyvpTKbFiugxFLtDfUCAJuI=; b=Ks7Ah9D3aR4H94/WEhxydW29DtYwgI2n1luwiucBUceFk7vLKXbzjC/e8CCBREvQq7A4Dj eYE5G11Mhub63JsTVCK8+Wvy+/eLDVY6Xxz2eM0ckmC5nJmcbRepgAY6ZuNrLRzdec9FTw FIABMBASA0qNUW0razYkrBcY28Jt+Kc= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Horatiu Vultur , Michael Walle Subject: [PATCH v4 06/13] ARM: dts: lan966x: add flexcom I2C nodes Date: Tue, 3 May 2022 00:41:20 +0200 Message-Id: <20220502224127.2604333-7-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220502224127.2604333-1-michael@walle.cc> References: <20220502224127.2604333-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add all I2C nodes of the flexcom IP blocks. The driver supports FIFO, DMA or both combined. But the latter isn't working correctly. Thus, skip the fifo-size property for now. DMA is doing single byte reads in this case. Keep the nodes disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index a37f2e58a1c2..342c8cee2b9a 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -120,6 +120,19 @@ spi0: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -158,6 +171,19 @@ spi1: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -213,6 +239,19 @@ spi2: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -251,6 +290,19 @@ spi3: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; dma0: dma-controller@e0068000 { @@ -308,6 +360,19 @@ spi4: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; timer0: timer@e008c000 {