From patchwork Thu Jul 28 14:34:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 594142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0E27C25B08 for ; Thu, 28 Jul 2022 14:36:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232885AbiG1OgW (ORCPT ); Thu, 28 Jul 2022 10:36:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232503AbiG1OfX (ORCPT ); Thu, 28 Jul 2022 10:35:23 -0400 Received: from mail.baikalelectronics.com (unknown [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E70C95E330; Thu, 28 Jul 2022 07:35:04 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 2A6C116DC; Thu, 28 Jul 2022 17:37:23 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 2A6C116DC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1659019043; bh=CP6uHqWycjI1e6CCd9dW0Oo+UWM6Fg4J8+x4zMfZXLs=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Qw5BYn9I465Bt8DicvjQfCa6NOtsyFVZc9kggopfGRjq0hUat8wv6Kk1fWfZrElsx rZiOdY0YuzLf/cTGcAh+Mka4+fdECAAwIGX1KKtp+JAxuXbjyXCgrmR0AnxL7JqNQd Lf4zlO3xF+DVpSGVa4fpiKnHkix0vG23OhTMB+5Q= Received: from localhost (192.168.53.207) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 28 Jul 2022 17:34:58 +0300 From: Serge Semin To: Rob Herring , Rob Herring , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= , Frank Li , Manivannan Sadhasivam , , , Subject: [PATCH v4 10/17] dt-bindings: PCI: dwc: Add dma-coherent property Date: Thu, 28 Jul 2022 17:34:20 +0300 Message-ID: <20220728143427.13617-11-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220728143427.13617-1-Sergey.Semin@baikalelectronics.ru> References: <20220728143427.13617-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the application memory access. They are used by the RP/EP PCIe buses (MWr/MWr TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all of them mainly involve the system memory and basically mean DMA we can expect the corresponding platforms can be designed in a way to make sure the transactions are cache-coherent. As such the DW PCIe DT-nodes can have the 'dma-coherent' property specified. Let's permit it in the DT-bindings then. Signed-off-by: Serge Semin --- Changelog v3: - This is a new patch created on v3 lap of the series. --- Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index f22fb01c9bd0..517f84d30198 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -160,6 +160,8 @@ properties: configuration space registers, Port Logic registers, DMA and iATU registers. This feature has been available since DWC PCIe v4.80a. + dma-coherent: true + additionalProperties: true definitions: