From patchwork Wed Aug 10 09:39:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 596511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E012C00140 for ; Wed, 10 Aug 2022 09:41:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232190AbiHJJlD (ORCPT ); Wed, 10 Aug 2022 05:41:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232216AbiHJJkt (ORCPT ); Wed, 10 Aug 2022 05:40:49 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E68D8D9E; Wed, 10 Aug 2022 02:40:44 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 27A9eeWm025503; Wed, 10 Aug 2022 04:40:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1660124440; bh=Q+F6U7EIc9QsxmhPltLHOiMZc4fyPzpeJVDzbd8Bvfs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=K8yBQHp1lX6g6Mh/CjaItw6BdrOCg7CfjP4Iwriy47Ro1WrXiQXpqxPgSTS/sBCit nhR/mKDo7guouKtKjRyNyZnnx87EpEL7EDRzh9m3bAPX7OvUwFmNTN8jIQllEDfp8s OnYhw7MUyAbUIUMlTyLkFQ8d5d9Heo6DssCdL51w= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 27A9eeB4023906 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Aug 2022 04:40:40 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 10 Aug 2022 04:40:39 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 10 Aug 2022 04:40:40 -0500 Received: from ubuntu.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 27A9e2Ps121822; Wed, 10 Aug 2022 04:40:33 -0500 From: Matt Ranostay To: CC: , , , Nishanth Menon , Matt Ranostay Subject: [PATCH RESEND 5/6] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Wed, 10 Aug 2022 02:39:59 -0700 Message-ID: <20220810094000.248487-5-mranostay@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220810094000.248487-1-mranostay@ti.com> References: <20220810094000.248487-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Cc: Vignesh Raghavendra Cc: Nishanth Menon Acked-by: Matt Ranostay Signed-off-by: Aswath Govindraju --- .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 791f235bd95f..aa75dc541842 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; &wkup_pmx0 { @@ -372,6 +378,22 @@ serdes0_pcie_link: phy@0 { }; }; +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + &mcu_mcan0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>;