From patchwork Thu Aug 11 02:58:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 596736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47289C25B08 for ; Thu, 11 Aug 2022 02:58:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233880AbiHKC6j (ORCPT ); Wed, 10 Aug 2022 22:58:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233843AbiHKC62 (ORCPT ); Wed, 10 Aug 2022 22:58:28 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94BB688DFC; Wed, 10 Aug 2022 19:58:26 -0700 (PDT) X-UUID: 7a584b2c33624a5880e21f525bca773a-20220811 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tS1bsJP4kxZ9hR4dR/gRP541fCFVSMhady9htG0xic4=; b=Nq5zlnWhq/SZnbYiWwtaOXwB8m/i5c/SPgGCjyTKP4xL2ZZzhi6rDkQtYAHABl/vK+GEwz/8qQ/2vebeVtDsqwPoy4TCO7v2RzHJ/WkToURBrllkWfGmdjbnk/HoDuEGIwalxGHQN0jcg7VUlzvIITGth2ZENKOpGCZRu0rVAZg=; X-CID-UNFAMILIAR: 1 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.9, REQID:177596bd-5a42-42dc-918f-40a055db9747, OB:0, LO B:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Releas e_Ham,ACTION:release,TS:100 X-CID-INFO: VERSION:1.1.9, REQID:177596bd-5a42-42dc-918f-40a055db9747, OB:0, LOB: 10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS9 81B3D,ACTION:quarantine,TS:100 X-CID-META: VersionHash:3d8acc9, CLOUDID:fe99fafc-9e71-4a0f-ba6b-417998daea35, C OID:d153ae9582ef,Recheck:0,SF:28|16|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 7a584b2c33624a5880e21f525bca773a-20220811 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 351040969; Thu, 11 Aug 2022 10:58:17 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 11 Aug 2022 10:58:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 11 Aug 2022 10:58:17 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen , MandyJH Liu CC: , , , , , , YC Hung , Allen-KH Cheng Subject: [PATCH v6 16/20] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes Date: Thu, 11 Aug 2022 10:58:09 +0800 Message-ID: <20220811025813.21492-17-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220811025813.21492-1-tinghan.shen@mediatek.com> References: <20220811025813.21492-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: YC Hung Add adsp node and adsp mailbox nodes for mt8195. Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index bbea0acff3d2f..f42d33414125f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -739,6 +739,43 @@ #clock-cells = <1>; }; + adsp: dsp@10803000 { + compatible = "mediatek,mt8195-dsp"; + reg = <0 0x10803000 0 0x1000>, + <0 0x10840000 0 0x40000>; + reg-names = "cfg", "sram"; + clocks = <&topckgen CLK_TOP_ADSP>, + <&clk26m>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_MAINPLL_D7_D2>, + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, + <&topckgen CLK_TOP_AUDIO_H>; + clock-names = "adsp_sel", + "clk26m_ck", + "audio_local_bus", + "mainpll_d7_d2", + "scp_adsp_audiodsp", + "audio_h"; + power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + status = "disabled"; + }; + + adsp_mailbox0: mailbox@10816000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10816000 0 0x1000>; + interrupts = ; + }; + + adsp_mailbox1: mailbox@10817000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10817000 0 0x1000>; + interrupts = ; + }; + afe: mt8195-afe-pcm@10890000 { compatible = "mediatek,mt8195-audio"; reg = <0 0x10890000 0 0x10000>;