From patchwork Sat Aug 20 19:48:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 598799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E7CEC32789 for ; Sat, 20 Aug 2022 19:48:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbiHTTso (ORCPT ); Sat, 20 Aug 2022 15:48:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231262AbiHTTsj (ORCPT ); Sat, 20 Aug 2022 15:48:39 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E708D1EC67 for ; Sat, 20 Aug 2022 12:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=gZ05criROPJOI6jRGySfjkdG7y3rkJwp0PpmApMj5Ys=; b=jzcLYikkjeq7hW3GTmFDGDqJ8e Hu5uQ5aqtTanUgR7nxi1ySPGb7XyzJecoEO6uyKRQd5cZl46nXQOUZk1wm03b/u4t6WGKS8GARqud kakL0cR/mn4ibwY+SkAl0pqpie/KTjmoYIJZt7KOlrM7rfa8OMEMyn/hno+MkYRdekYw=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48a-RE; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 10/11] DT: timer: Convert marvell,orion-timer.txt to YAML Date: Sat, 20 Aug 2022 21:48:03 +0200 Message-Id: <20220820194804.3352415-11-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Andrew Lunn --- .../bindings/timer/marvell,orion-timer.txt | 16 ------ .../bindings/timer/marvell,orion-timer.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/marvell,orion-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt deleted file mode 100644 index cd1a0c256f94..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -Marvell Orion SoC timer - -Required properties: -- compatible: shall be "marvell,orion-timer" -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 and Timer1 -- clocks: phandle of timer reference clock (tclk) - -Example: - timer: timer { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml new file mode 100644 index 000000000000..330bb3cd9c26 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/marvell,orion-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion Timer bindings + +maintainers: + - Andrew Lunn + +properties: + $nodename: + pattern: '^timer@[a-f0-9]+$' + + compatible: + const: marvell,orion-timer + + reg: + description: + Base address of the timer register starting with TIMERS CONTROL register + maxItems: 1 + + interrupts: + description: + Should contain the interrupts for Timer0 and Timer1 + minItems: 2 + maxItems: 2 + + clocks: + description: + phandle of timer reference clock (tclk) + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; +...