diff mbox series

[4/4] arm64: dts: imx8mp-evk: enable HDMI

Message ID 20220826192932.3217260-4-l.stach@pengutronix.de
State New
Headers show
Series None | expand

Commit Message

Lucas Stach Aug. 26, 2022, 7:29 p.m. UTC
Enable the DT nodes for HDMI TX and PHY and add the pinctrl for the few
involved pins that are configurable.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 27 ++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Luca Ceresoli March 2, 2023, 3:35 p.m. UTC | #1
Hello Lucas,

On Fri, 26 Aug 2022 21:29:32 +0200
Lucas Stach <l.stach@pengutronix.de> wrote:

> Enable the DT nodes for HDMI TX and PHY and add the pinctrl for the few
> involved pins that are configurable.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

I'm joining late to this party... Is this the latest version of this
series? I haven't found any more recent, but if it is not the case
would you point me to the most recent one please?

> +	pinctrl_hdmi: hdmigrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c3
> +			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c3

Is the low nibble (0x3) right?BIT(0) is reserved according too the
reference manual.

Also, all the non-reserved bits in that nibble are bits 1 and 2, which
set the drive strength. For an I2C line it seems that the minimum drive
strength (0x0) should be enough for an I2C line: with any drive
strength setting the supported frequency is >= 65 MHz.

> +			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x19
> +			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x19

Here as well, bits 0 and 3 are reserved.

Best regards,
Luca
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index f6b017ab5f53..f3180c90709e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -213,6 +213,20 @@  &flexcan2 {
 	status = "disabled";/* can2 pin conflict with pdm */
 };
 
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -350,6 +364,10 @@  &i2c5 {
 	 */
 };
 
+&lcdif3 {
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -481,6 +499,15 @@  MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140
 		>;
 	};
 
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c3
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x19
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x19
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2