From patchwork Tue Aug 30 16:58:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 601622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93F82ECAAD1 for ; Tue, 30 Aug 2022 17:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231318AbiH3RAF (ORCPT ); Tue, 30 Aug 2022 13:00:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231286AbiH3Q7j (ORCPT ); Tue, 30 Aug 2022 12:59:39 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FA14B603B for ; Tue, 30 Aug 2022 09:59:35 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id t129so11930650pfb.6 for ; Tue, 30 Aug 2022 09:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=+nFPGJL9DaKSTkpdD0XYV1f18/EerKy4FdCtQJJTq78=; b=lfYKqROpmRlpL3DqSB3zms6UXIsfrOhcyDkVHVwWGZBmQJlIujKVnDe0bdyC6sgfRj ftdTGzaBqQWGuuFzl8lPLDYvJjVzlxtjCN+BwQZ7TBAYHiuT4y4OC3g+75WjH9btWhB5 8VdqYpb4VvouExkYDPiys+cnmABpX+b09ekFCYrpw3l46AZtwG/HNFXGGzZGfWBcKiUz XjnV4OfrLh1NkRG3EcSURvdtK36MmvcpRG448GOo51Q2qqp1/CDjK+aC8qFeh27tdUmi hJnXjjJWUZpkuKXakafiA+diQVRNxW72lCGXGj5UGubrUXlirQvHdqqq2CFiSp+jCDX9 fKpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=+nFPGJL9DaKSTkpdD0XYV1f18/EerKy4FdCtQJJTq78=; b=xnWph+HcAOTKeM5bt71Xk9uTvAqbkutUxunRJfhO288exoi3qe+n/DyF0ZCJgBJ+m+ zroRZn8XzF6Cx34oZZMLW5hN1HzYrTEeHeBeK8QvhO+SjE/nqo8NPmV5T/Z4JXEQ4RuN p6Ql6Ig5vh+7B/P+FU5uIrw38x2b9Xgf9v5CrvIa8BxHLmjppWTNpnQ862Scc9U1rl4Q +V0U6jNDcMloXKRgPq+iFBCrHZXZZwWtQtlED4DBnQCMyc+KNvj6wsTszI5Zfbj4cFGk 38sto2hFDzZOdLtV0kxUpoEeA5URQfSLQFs6tHokyxD/wchGw6xiv/3Abe5l7vUXKvO0 Y/yg== X-Gm-Message-State: ACgBeo3HIOPWxPgV6mg0eoGC7Tm/jWAWePikCjsJI0JkG0YrPDzNX54b VgBnJiCC5ydXHZCixN9tQcQT X-Google-Smtp-Source: AA6agR4UjtYECqhqxWpR8YXyyfnUouq0WDy0qcGXLSRGaEeA4KOLING/BPaATbhjwzc+TK8sBdHqCQ== X-Received: by 2002:a62:ed08:0:b0:537:17a6:57aa with SMTP id u8-20020a62ed08000000b0053717a657aamr22483376pfh.6.1661878773041; Tue, 30 Aug 2022 09:59:33 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.234]) by smtp.gmail.com with ESMTPSA id n59-20020a17090a5ac100b001f510175984sm8841261pji.41.2022.08.30.09.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 09:59:32 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 09/11] dt-bindings: PCI: qcom-ep: Define clocks per platform Date: Tue, 30 Aug 2022 22:28:15 +0530 Message-Id: <20220830165817.183571-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> References: <20220830165817.183571-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation of adding the bindings for future SoCs, let's define the clocks per platform. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 51 ++++++++++++------- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index b728ede3f09f..a15e71491722 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -9,9 +9,6 @@ title: Qualcomm PCIe Endpoint Controller binding maintainers: - Manivannan Sadhasivam -allOf: - - $ref: "pci-ep.yaml#" - properties: compatible: const: qcom,sdx55-pcie-ep @@ -35,24 +32,10 @@ properties: - const: mmio clocks: - items: - - description: PCIe Auxiliary clock - - description: PCIe CFG AHB clock - - description: PCIe Master AXI clock - - description: PCIe Slave AXI clock - - description: PCIe Slave Q2A AXI clock - - description: PCIe Sleep clock - - description: PCIe Reference clock + maxItems: 7 clock-names: - items: - - const: aux - - const: cfg - - const: bus_master - - const: bus_slave - - const: slave_q2a - - const: sleep - - const: ref + maxItems: 7 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -112,6 +95,36 @@ required: - reset-names - power-domains +allOf: + - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx55-pcie-ep + then: + properties: + clocks: + maxItems: 7 + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Sleep clock + - description: PCIe Reference clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: sleep + - const: ref + unevaluatedProperties: false examples: