From patchwork Sat Sep 10 12:47:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 604638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0667C6FA86 for ; Sat, 10 Sep 2022 12:47:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229702AbiIJMrQ (ORCPT ); Sat, 10 Sep 2022 08:47:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229552AbiIJMrN (ORCPT ); Sat, 10 Sep 2022 08:47:13 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 219AF57E00 for ; Sat, 10 Sep 2022 05:47:11 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id f14so6284755lfg.5 for ; Sat, 10 Sep 2022 05:47:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Xnrwle//1aq5NGhF/qMEZvbwwoMwpjLog3bunzgx6rM=; b=BVd/bJ7kuaUOUaXMcU3dQZTD6lIj6NGmKFCMIH5ED55WCea78YSjfASq9DfQcf6d1q /6JbDNWgopU84NuCLP0JLoEhzqTc9IMaD6z8XeVB2FxNvh27Djbo3U8/ymNglT8fV+44 OQ+u9ZXS4ojSAuB0FuBdDY3HW6yodwsxcCuA6E2iaIZBgxO9cIuE7urMT8JD5pTB8vsj ZOFJtDQNTfWJBTpdNu9X607Xn8DaNfASia4uRZIz5Tlk8VgN19TWQFL6dgUfVGiNjFhi yUEOmGPLsFNGLPN2m9MPMwLrsMvJcMTKZ4JkxuAxLCwxXiX9myaZf8WozF3qFApWIKY1 iIdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Xnrwle//1aq5NGhF/qMEZvbwwoMwpjLog3bunzgx6rM=; b=bB3R7Jmz9U6WruIyYZu0XqsZoIMLABeKJSADQqi7BgnXeKyyHwBJCfmDTyDv8RaAvV lcUmxDUw/G8zafPjQIc/jI8f0AS5R9dTJpYVVnXOzc19pO3r9a80/s6vMW4wZFrVDl5X D+xxjEezGPSn8tx6+bhLjdKqiuPYR9WH2rLCa7muKCz6inh4c3O6x5PmFV3uHX6KgJ0a N3htU29s39Z3irW8dC7UECGJjJ/1d/PRzRR9/SuXYKeEYsjqg5YmBVzplgiXUPVfe1Mg yat6v6saJefk2UC3sY1+8wgSK1v+XXYf+IX6489GLrXDzX4sl8FzYjM/Q8b555Zbm2ZC QOfQ== X-Gm-Message-State: ACgBeo3ocyz5HVKBDDhGPwIdYWOkblzHqbZvoVyio3jow5a0/HB/WLYn 2tNNf9gCYxHqFkiDhScfY+VS1LZTMtNzMQ== X-Google-Smtp-Source: AA6agR6s148d4YerVeBrqBSEgZ0fxuXqADDlmf/69Y+9zvQwmWUbnDleLVGwNxVrSGTTZpEEJ4sVrw== X-Received: by 2002:a05:6512:31cc:b0:494:6815:a81b with SMTP id j12-20020a05651231cc00b004946815a81bmr6365824lfe.511.1662814029971; Sat, 10 Sep 2022 05:47:09 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k14-20020a2e920e000000b002677a3ad1d9sm327463ljg.76.2022.09.10.05.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Sep 2022 05:47:09 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 09/10] arm64: dts: qcom: msm8916: specify per-sensor calibration cells Date: Sat, 10 Sep 2022 15:47:00 +0300 Message-Id: <20220910124701.4060321-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> References: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 70 ++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 48bc2e09128d..d2cce8f75fb6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,57 @@ qfprom: qfprom@5c000 { reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + tsens_s0_p1: s0_p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + tsens_s0_p2: s0_p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; + }; + tsens_s1_p1: s1_p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1_p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2_p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + tsens_s2_p2: s2_p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + tsens_s3_p1: s3_p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + tsens_s3_p2: s3_p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + tsens_s4_p1: s4_p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + tsens_s4_p2: s4_p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +519,20 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2"; #qcom,sensors = <5>; interrupts = ; interrupt-names = "uplow";