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[88.156.142.199]) by smtp.gmail.com with ESMTPSA id y5-20020a05651c106500b002770a9ed61bsm1327875ljm.66.2022.11.07.10.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 10:59:34 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] ARM: dts: qcom-apq8060: align TLMM pin configuration with DT schema Date: Mon, 7 Nov 2022 19:59:31 +0100 Message-Id: <20221107185931.22075-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107185931.22075-1-krzysztof.kozlowski@linaro.org> References: <20221107185931.22075-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski --- .../arm/boot/dts/qcom-apq8060-dragonboard.dts | 126 +++++++----------- 1 file changed, 51 insertions(+), 75 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 0baf202a82ba..7a4c59e04af6 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -789,28 +789,24 @@ &sdcc5 { &tlmm { /* eMMC pins, all 8 data lines connected */ - dragon_sdcc1_pins: sdcc1 { - mux { - pins = "gpio159", "gpio160", "gpio161", - "gpio162", "gpio163", "gpio164", - "gpio165", "gpio166", "gpio167", - "gpio168"; - function = "sdc1"; - }; - clk { + dragon_sdcc1_pins: sdcc1-state { + clk-pins { pins = "gpio167"; /* SDC1 CLK */ + function = "sdc1"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "gpio168"; /* SDC1 CMD */ + function = "sdc1"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { /* SDC1 D0 to D7 */ pins = "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166"; + function = "sdc1"; drive-strength = <10>; bias-pull-up; }; @@ -820,18 +816,18 @@ data { * The SDCC3 pins are hardcoded (non-muxable) but need some pin * configuration. */ - dragon_sdcc3_pins: sdcc3 { - clk { + dragon_sdcc3_pins: sdcc3-state { + clk-pins { pins = "sdc3_clk"; drive-strength = <8>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc3_cmd"; drive-strength = <8>; bias-pull-up; }; - data { + data-pins { pins = "sdc3_data"; drive-strength = <8>; bias-pull-up; @@ -839,101 +835,82 @@ data { }; /* Second SD card slot pins */ - dragon_sdcc5_pins: sdcc5 { - mux { - pins = "gpio95", "gpio96", "gpio97", - "gpio98", "gpio99", "gpio100"; - function = "sdc5"; - }; - clk { + dragon_sdcc5_pins: sdcc5-state { + clk-pins { pins = "gpio97"; /* SDC5 CLK */ + function = "sdc5"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "gpio95"; /* SDC5 CMD */ + function = "sdc5"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { /* SDC5 D0 to D3 */ pins = "gpio96", "gpio98", "gpio99", "gpio100"; + function = "sdc5"; drive-strength = <10>; bias-pull-up; }; }; - dragon_gsbi3_i2c_pins: gsbi3_i2c { - mux { - pins = "gpio43", "gpio44"; - function = "gsbi3"; - }; - pinconf { - pins = "gpio43", "gpio44"; - drive-strength = <8>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; + dragon_gsbi3_i2c_pins: gsbi3-i2c-state { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + drive-strength = <8>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; }; - dragon_gsbi8_i2c_pins: gsbi8_i2c { - mux { - pins = "gpio64", "gpio65"; - function = "gsbi8"; - }; - pinconf { - pins = "gpio64", "gpio65"; - drive-strength = <16>; - /* These have external pull-up 2.2kOhm to 1.8V */ - bias-disable; - }; + dragon_gsbi8_i2c_pins: gsbi8-i2c-state { + pins = "gpio64", "gpio65"; + function = "gsbi8"; + drive-strength = <16>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; }; - dragon_gsbi12_i2c_pins: gsbi12_i2c { - mux { - pins = "gpio115", "gpio116"; - function = "gsbi12"; - }; - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <16>; - /* These have external pull-up 4.7kOhm to 1.8V */ - bias-disable; - }; + dragon_gsbi12_i2c_pins: gsbi12-i2c-state { + pins = "gpio115", "gpio116"; + function = "gsbi12"; + drive-strength = <16>; + /* These have external pull-up 4.7kOhm to 1.8V */ + bias-disable; }; /* Primary serial port uart 0 pins */ - dragon_gsbi12_serial_pins: gsbi12_serial { - mux { - pins = "gpio117", "gpio118"; - function = "gsbi12"; - }; - tx { + dragon_gsbi12_serial_pins: gsbi12-serial-state { + tx-pins { pins = "gpio117"; + function = "gsbi12"; drive-strength = <8>; bias-disable; }; - rx { + rx-pins { pins = "gpio118"; + function = "gsbi12"; drive-strength = <2>; bias-pull-up; }; }; - dragon_ebi2_pins: ebi2 { + dragon_ebi2_pins: ebi2-state { /* * Pins used by EBI2 on the Dragonboard, actually only * CS2 is used by a real peripheral. CS0 is just * routed to a test point. */ - mux0 { + mux0-pins { pins = /* "gpio39", CS1A_N this is not good to mux */ "gpio40", /* CS2A_N */ "gpio134"; /* CS0_N testpoint TP29 */ function = "ebi2cs"; }; - mux1 { + mux1-pins { pins = /* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */ "gpio123", "gpio124", "gpio125", "gpio126", @@ -951,22 +928,21 @@ mux1 { }; /* Interrupt line for the KXSD9 accelerometer */ - dragon_kxsd9_gpios: kxsd9 { - irq { - pins = "gpio57"; /* IRQ line */ - bias-pull-up; - }; + dragon_kxsd9_gpios: kxsd9-state { + pins = "gpio57"; /* IRQ line */ + function = "gpio"; + bias-pull-up; }; - dragon_tma340_gpios: tma340 { - reset { + dragon_tma340_gpios: tma340-state { + reset-pins { /* RESET line, TS_ATTN, WAKE_CTP */ pins = "gpio58"; function = "gpio"; drive-strength = <6>; bias-disable; }; - irq { + irq-pins { pins = "gpio61"; /* IRQ line */ function = "gpio"; drive-strength = <2>;