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Fri, 30 Dec 2022 00:02:06 +0000 Received: from DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::2b95:1fe4:5d8f:22fb]) by DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::2b95:1fe4:5d8f:22fb%8]) with mapi id 15.20.5944.016; Fri, 30 Dec 2022 00:02:06 +0000 From: Sean Anderson To: Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Camelia Alexandra Groza , Madalin Bucur , Bagas Sanjaya , Rob Herring , Ioana Ciornei , linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Sean Anderson , Li Yang , Shawn Guo Subject: [PATCH v9 10/10] arm64: dts: ls1088ardb: Add serdes bindings Date: Thu, 29 Dec 2022 19:01:39 -0500 Message-Id: <20221230000139.2846763-11-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20221230000139.2846763-1-sean.anderson@seco.com> References: <20221230000139.2846763-1-sean.anderson@seco.com> X-ClientProxiedBy: BL1P221CA0016.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:2c5::29) To DB9PR03MB8847.eurprd03.prod.outlook.com (2603:10a6:10:3dd::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB9PR03MB8847:EE_|PAWPR03MB9788:EE_ X-MS-Office365-Filtering-Correlation-Id: 310a2a0a-7e81-49c2-d298-08dae9f91677 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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I have tested the QSGMII ports as well as the two 10G ports. The SFP slot is now fully supported, instead of being modeled as a fixed-link. Linux hangs around when the serdes is initialized if the si5341 is enabled with the in-tree driver, so I have modeled it as a two fixed clocks instead. There are a few registers in the QIXIS FPGA which control the SFP GPIOs; I have modeled them as discrete GPIO controllers for now. I never saw the AQR105 interrupt fire; not sure what was going on, but I have removed it to force polling. To enable serdes support, the DPC needs to set the macs to MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be converted at once. Additionally, in order to change interface types, the MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE. Signed-off-by: Sean Anderson --- Changes in v9: - Add fsl,unused-lanes-reserved to allow a gradual transition, depending on the mac link type. - Remove unused clocks - Fix some phy mode node names - phy-type -> fsl,phy Changes in v8: - Rename serdes phy handles like the LS1046A - Add SFP slot binding - Fix incorrect lane ordering (it's backwards on the LS1088A just like it is in the LS1046A). - Fix duplicated lane 2 (it should have been lane 3). - Fix incorrectly-documented value for XFI1. - Remove interrupt for aquantia phy. It never fired for whatever reason, preventing the link from coming up. - Add GPIOs for QIXIS FPGA. - Enable MAC1 PCS - Remove si5341 binding Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 162 +++++++++++++++++- 1 file changed, 160 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 1bfbce69cc8b..d75cf52a7616 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -10,17 +10,137 @@ /dts-v1/; +#include +#include + #include "fsl-ls1088a.dtsi" / { model = "LS1088A RDB Board"; compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; + + clocks { + clk_100mhz: clock-100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk_156mhz: clock-156mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + }; + + sfp_slot: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + los-gpios = <&los_stat 5 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&los_stat 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&brdcfg9 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&serdes1 { + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + fsl,unused-lanes-reserved; + status = "okay"; + + /* + * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin + * numbers are _reversed_. + */ + serdes1_A: phy@0 { + #phy-cells = <0>; + reg = <0>; + + /* QSGb */ + qsgmii-0 { + fsl,pccr = <0x9>; + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_B: phy@1 { + #phy-cells = <0>; + reg = <1>; + + /* QSGa */ + qsgmii-1 { + fsl,pccr = <0x9>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; + + serdes1_C: phy@2 { + #phy-cells = <0>; + reg = <2>; + + /* SG1 */ + sgmii-2 { + fsl,pccr = <0x8>; + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* + * XFI1 + * Table 23-1 and section 23.5.16.4 disagree; this reflects the + * table. + * + * fsl,cfg is documented as 1, but it is set to 2 by the RCW! + * This is the same as the LS1046A. + */ + xfi-0 { + fsl,pccr = <0xb>; + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,type = ; + }; + }; + + serdes1_D: phy@3 { + #phy-cells = <0>; + reg = <3>; + + /* SG2 */ + sgmii-3 { + fsl,pccr = <0x8>; + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + + /* XFI2 */ + xfi-1 { + fsl,pccr = <0xb>; + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,type = ; + }; + }; +}; + +&dpmac1 { + managed = "in-band-status"; + pcs-handle = <&pcs1>; + phys = <&serdes1_C>; + sfp = <&sfp_slot>; }; &dpmac2 { phy-handle = <&mdio2_aquantia_phy>; phy-connection-type = "10gbase-r"; + managed = "in-band-status"; pcs-handle = <&pcs2>; + phys = <&serdes1_D>; }; &dpmac3 { @@ -28,6 +148,7 @@ &dpmac3 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_0>; + phys = <&serdes1_A>; }; &dpmac4 { @@ -35,6 +156,7 @@ &dpmac4 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_1>; + phys = <&serdes1_A>; }; &dpmac5 { @@ -42,6 +164,7 @@ &dpmac5 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_2>; + phys = <&serdes1_A>; }; &dpmac6 { @@ -49,6 +172,7 @@ &dpmac6 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs3_3>; + phys = <&serdes1_A>; }; &dpmac7 { @@ -56,6 +180,7 @@ &dpmac7 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_0>; + phys = <&serdes1_B>; }; &dpmac8 { @@ -63,6 +188,7 @@ &dpmac8 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_1>; + phys = <&serdes1_B>; }; &dpmac9 { @@ -70,6 +196,7 @@ &dpmac9 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_2>; + phys = <&serdes1_B>; }; &dpmac10 { @@ -77,6 +204,7 @@ &dpmac10 { phy-connection-type = "qsgmii"; managed = "in-band-status"; pcs-handle = <&pcs7_3>; + phys = <&serdes1_B>; }; &emdio1 { @@ -128,7 +256,6 @@ &emdio2 { mdio2_aquantia_phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; reg = <0x0>; }; }; @@ -171,6 +298,12 @@ rtc@51 { interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>; }; }; + + sfp_i2c: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; }; }; @@ -185,8 +318,29 @@ nand@0,0 { }; fpga: board-control@2,0 { - compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis", + "simple-bus"; reg = <0x2 0x0 0x0000100>; + ranges = <0x0 0x2 0x0 0x0000100>; + + los_stat: gpio-controller@1d { + #gpio-cells = <2>; + compatible = "fsl,fpga-qixis-los-stat", + "ni,169445-nand-gpio"; + reg = <0x1d 0x1>; + reg-names = "dat"; + no-output; + }; + + brdcfg9: gpio-controller@59 { + #gpio-cells = <2>; + compatible = "fsl,fpga-qixis-brdcfg9", + "ni,169445-nand-gpio"; + reg = <0x59 0x1>; + reg-names = "dat"; + }; }; }; @@ -203,6 +357,10 @@ &esdhc { status = "okay"; }; +&pcs_mdio1 { + status = "okay"; +}; + &pcs_mdio2 { status = "okay"; };