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[v3,2/2] dt-bindings: opp: opp-v2-kryo-cpu: enlarge opp-supported-hw maximum

Message ID 20230123193422.15972-2-ansuelsmth@gmail.com
State Accepted
Commit ba38f3cbe7db2cec802c6d60e2bef57a3ff095a4
Headers show
Series [v3,1/2] dt-bindings: cpufreq: qcom-cpufreq-nvmem: make cpr bindings optional | expand

Commit Message

Christian Marangi Jan. 23, 2023, 7:34 p.m. UTC 
Enlarge opp-supported-hw maximum value. In recent SoC we started
matching more bit and we currently match mask of 112. The old maximum of
7 was good for old SoC that didn't had complex id, but now this is
limiting and we need to enlarge it to support more variants.

Document all the various mask that can be used and limit them to only
reasonable values instead of using a generic maximum limit.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---

Changes v3:
- Fix dt_binding_check for missing 0x5 and 0x6 value
Changes v2:
- Document additional bit format

 .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
index b4947b326773..bbbad31ae4ca 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
@@ -50,12 +50,22 @@  patternProperties:
       opp-supported-hw:
         description: |
           A single 32 bit bitmap value, representing compatible HW.
-          Bitmap:
+          Bitmap for MSM8996 format:
           0:  MSM8996, speedbin 0
           1:  MSM8996, speedbin 1
           2:  MSM8996, speedbin 2
-          3-31:  unused
-        maximum: 0x7
+          3:  MSM8996, speedbin 3
+          4-31:  unused
+
+          Bitmap for MSM8996SG format (speedbin shifted of 4 left):
+          0-3:  unused
+          4:  MSM8996SG, speedbin 0
+          5:  MSM8996SG, speedbin 1
+          6:  MSM8996SG, speedbin 2
+          7-31:  unused
+        enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
+               0x9, 0xd, 0xe, 0xf,
+               0x10, 0x20, 0x30, 0x70]
 
       clock-latency-ns: true