From patchwork Tue Jan 24 12:47:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 646156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E31DC54E94 for ; Tue, 24 Jan 2023 12:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234076AbjAXMtC (ORCPT ); Tue, 24 Jan 2023 07:49:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234100AbjAXMsX (ORCPT ); Tue, 24 Jan 2023 07:48:23 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA87811179 for ; Tue, 24 Jan 2023 04:47:44 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so12749028wma.1 for ; Tue, 24 Jan 2023 04:47:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bmxwKRwgMkvDoX/KnOxwn8Oad6lb6c+WQifHQxcxOEc=; b=FYiBwKa35DWkzQ7j81Fy1fx9TUTExvKgXy2CCwctwSdzBVeheK+IttrEAC/ETe1EeK W6pTqY6vdQIu5OeMoBi5ykV0bNXQEQcNlYLhEYl/c/hrjXANIeZJBSVq53+wCX20yCoX yyBHuad2Xj6DD7X6AVd0P370eE5eOtgxau8Q+6ib8pXb8Ky3+mPDj63Ek5P6dieIhWy2 +rQ65PjSPosaZRvZRLx8jp6HXLm6WdvchQifiY0vM22iny8Ak4zyhJw3y8OsiJ9xXJ2+ PeFG3pWzrbd3Blz/YIqBS1GCtPU/bpGc6SYAS/5ZXC1L9Fhnzv89cxz59co5dW1obqnN PiIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bmxwKRwgMkvDoX/KnOxwn8Oad6lb6c+WQifHQxcxOEc=; b=D2K9wRLfMKqG8hgFxRlSgd6Y3injsXdQxVQuCtc0q2MjZ1izs4RZktuVLfrCreMGhL RM/SFX/TO1XJAoLPl1h84KsZxCUge0bY3EYK+sPg7xqoCJxJMcYCS31uyuZLzp5pY2Nc JiEDaJjIZZ1U6oAMah/ApDqIUp0Mwp2Dbz1AiET7KZRIOzytpcdXnheAPYUPm9Sz68e3 O8VUD46UbB7K8FgJLomCV5vqvLuaQXdlXfrkihEn80rAXufnOG7Y1pqcbjSPCSMFiykU BotjWx1hpRhL/5Jg0P6hL7Hm3CpBR3CmfA23rZV9fd2M+olceCEOCDQysMwFL7yq9p/7 Qj8A== X-Gm-Message-State: AFqh2krLzx7REO7e2biH4JeWItVSv2oAs8xVdw9ckUM53728ZLdriVV/ 74ziBEkxwmWK9xgZL3K+TVlBrg== X-Google-Smtp-Source: AMrXdXvAgpKt63Oz3NCXx6cY0Sb1j3ZgYXfQIwSjkUsBwo/uBUEf/kEPiUkYZk/vC91kl4DwXQ+Dog== X-Received: by 2002:a05:600c:6001:b0:3da:f80a:5e85 with SMTP id az1-20020a05600c600100b003daf80a5e85mr27274855wmb.26.1674564460550; Tue, 24 Jan 2023 04:47:40 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id a5-20020a5d5705000000b002bdbde1d3absm1766840wrv.78.2023.01.24.04.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 04:47:39 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org, Neil Armstrong Subject: [PATCH v5 12/12] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes Date: Tue, 24 Jan 2023 14:47:14 +0200 Message-Id: <20230124124714.3087948-13-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124124714.3087948-1-abel.vesa@linaro.org> References: <20230124124714.3087948-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa --- This patch does not have a v3, but since it is now part of the same patchset with the controller and the phy drivers patches, I had to bump the version to 4. The v4 was here: https://lore.kernel.org/all/20230118230526.1499328-3-abel.vesa@linaro.org/ Changes since v4: * moved here the pinctrl properties and out of dtsi file Changes since v2: * none Changes since v1: * ordered pcie related nodes alphabetically in MTP dts * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes * dropped the child node from the phy nodes, like Johan suggested, and updated to use the sc8280xp binding scheme * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy to "nocsr" * reordered all pcie nodes properties to look similar to the ones from sc8280xp arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 37 +++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 81fcbdc6bdc4..31e039f10a1b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -359,6 +359,43 @@ vreg_l3g_1p2: ldo3 { }; }; +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12";