From patchwork Tue Feb 7 11:40:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 651432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15426C636CC for ; Tue, 7 Feb 2023 11:41:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231685AbjBGLlD (ORCPT ); Tue, 7 Feb 2023 06:41:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231691AbjBGLlA (ORCPT ); Tue, 7 Feb 2023 06:41:00 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2679418B20 for ; Tue, 7 Feb 2023 03:40:51 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso12971118wms.0 for ; Tue, 07 Feb 2023 03:40:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nJj7gGBxaDtI7Dk7IzDCWGMAsOchBp2v8Bo2jum9xMw=; b=NbuQs2Kw0EntfnKW3njcuFFnkz7c+HfDtwA9VdonyQA9sB9TXo1sdFRcZwL7U+gf+X 7p2+fDEFxrpM06BO0eB/YeVxKEejuEe/CYTHrqYXcgNMjWUom0SizXi6v/CDGN24ZzaW 9DcAOhc/MbcrlB0bm6hMj/uPFWN44iN7mJD4K7sj7i5224J+GDU36le16lU0VDGCsJ3v wm2/f70PbO8YIayJL7q3s+CQeL9bKsTFDqjYXZxN0xHS+Vu8NviJ+FijTWEDPEbbLwWG qrIpa1wW63BhvSzCO3i9g3uoFe82dyS4+ypWoZFdzSS9aTMsuCXym7QDDOtPRYcrqqaD Sg5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nJj7gGBxaDtI7Dk7IzDCWGMAsOchBp2v8Bo2jum9xMw=; b=RsSa0L+4dpBPZGkKbSUPvOfmjdQQlkydFlZ5iTFiZBdKf2gL1zpPR5dxRe4XxUPQwz SJUlHkkub8C2nqmOqJMFJGO2bkb08DunAIYTWaOfuTSCc2h2XC5a7/uxixytYyK6OAEX BEcIF27eOngn8cuuQ2qOfl72PH2TBNy6hPvwtlGeOVDEBFpTe36d7cI+C8hEevszuwZ6 qpsZ2xAuIzcMBOhWRoGfQllMC2MNHbGpSnII7Y9n5gLJ9As336GB3NtQFA1CKJSvy2Zv 5pfBa1fRfT1TAwk/tf3Mp7KOGHpYG9IzlSa2xGZpXxBYOVdISxquHtPyEbJ73iaiwiz+ hW6Q== X-Gm-Message-State: AO0yUKVgxnumETLUHVKMwJ+tgIloRYX9xHrvxNzkfMYTmd8OHpheS1JN Mlo2oJ6q9sOpCNaNqn2ufeOxdA== X-Google-Smtp-Source: AK7set8tq37XnI2V3z9QG6lYxxWA+N7NlrZB9jLcWpWnmDBkNzCGYpp2CEN30gQhd92aUgmPhsCwew== X-Received: by 2002:a05:600c:80f:b0:3d2:2d2a:d581 with SMTP id k15-20020a05600c080f00b003d22d2ad581mr2797658wmp.30.1675770049373; Tue, 07 Feb 2023 03:40:49 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id c7-20020a05600c0ac700b003d1d5a83b2esm18326005wmr.35.2023.02.07.03.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 03:40:48 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v5 4/6] phy: qcom-qmp: pcs-usb: Add v6 register offsets Date: Tue, 7 Feb 2023 13:40:22 +0200 Message-Id: <20230207114024.944314-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230207114024.944314-1-abel.vesa@linaro.org> References: <20230207114024.944314-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa --- The v4 version of this patch was here: https://lore.kernel.org/all/20230202132511.3983095-5-abel.vesa@linaro.org/ Changes since v4: * none Changes since v3: * none Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 + .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h | 31 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 82b46f4c6df0..1cf643cb0218 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -26,6 +26,7 @@ #include "phy-qcom-qmp-pcs-misc-v3.h" #include "phy-qcom-qmp-pcs-usb-v4.h" #include "phy-qcom-qmp-pcs-usb-v5.h" +#include "phy-qcom-qmp-pcs-usb-v6.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h new file mode 100644 index 000000000000..9510e63ba9d8 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_ +#define QCOM_PHY_QMP_PCS_USB_V6_H_ + +/* Only for QMP V6 PHY - USB3 have different offsets than V5 */ +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4 +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8 +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8 +#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc +#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90 +#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc +#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec + +#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 +#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c +#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 +#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44 + +#endif