From patchwork Fri Jul 7 05:26:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 700211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C497BC001DE for ; Fri, 7 Jul 2023 05:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232605AbjGGF0o (ORCPT ); Fri, 7 Jul 2023 01:26:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232505AbjGGF0b (ORCPT ); Fri, 7 Jul 2023 01:26:31 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39C341FC9; Thu, 6 Jul 2023 22:26:24 -0700 (PDT) X-UUID: cbbdd57c1c8611eeb20a276fd37b9834-20230707 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EgTVB8/wFgscxLDYs3qg9WMPyo6Fp8L2xH8FV1ZxS8Y=; b=u10n2+cZ99Q7+RD9JI6aMXSMAxcLVhxZ1+pE+/9xttqkE3qBDpmhx1Yxcx3Gzl0KcOL2v1vOtymC01jV/kpUxdQ6Nl7/nJIW2l1/C/kBiXp7/FWp29Outs3KwoGYidSpAlCXrp16rcVl4jUHWmHBIzUrqakG8vd7Fyrigi2k+FE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.27, REQID:0622ba51-2513-48ff-9dee-ded7081a4d14, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.27, REQID:0622ba51-2513-48ff-9dee-ded7081a4d14, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:01c9525, CLOUDID:df6caa0d-26a8-467f-b838-f99719a9c083, B ulkID:230707132617KIDHYEMW,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SDM, TF_CID_SPAM_ASC, TF_CID_SPAM_FAS, TF_CID_SPAM_FSD, TF_CID_SPAM_SNR X-UUID: cbbdd57c1c8611eeb20a276fd37b9834-20230707 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 509429975; Fri, 07 Jul 2023 13:26:16 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 7 Jul 2023 13:26:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 7 Jul 2023 13:26:16 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" CC: , , , , , Subject: [PATCH v14 12/12] arm64: dts: mediatek: mt8195: Add SCP 2nd core Date: Fri, 7 Jul 2023 13:26:12 +0800 Message-ID: <20230707052612.27521-13-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230707052612.27521-1-tinghan.shen@mediatek.com> References: <20230707052612.27521-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rewrite the MT8195 SCP device node as a cluster and add the SCP 2nd core in it. Since the SCP device node is changed to multi-core structure, enable SCP cluster to enable probing SCP core 0. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 34 ++++++++++++++----- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 37a3e9de90ff..4584077d3a4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -991,7 +991,11 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; -&scp { +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { status = "okay"; firmware-name = "mediatek/mt8195/scp.img"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 48b72b3645e1..7809118f74fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -922,14 +922,30 @@ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; }; - scp: scp@10500000 { - compatible = "mediatek,mt8195-scp"; - reg = <0 0x10500000 0 0x100000>, - <0 0x10720000 0 0xe0000>, - <0 0x10700000 0 0x8000>; - reg-names = "sram", "cfg", "l1tcm"; - interrupts = ; + scp_cluster: scp@10500000 { + compatible = "mediatek,mt8195-scp-dual"; + reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; + reg-names = "cfg", "l1tcm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10500000 0x100000>; status = "disabled"; + + scp_c0: scp@0 { + compatible = "mediatek,scp-core"; + reg = <0x0 0xa0000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; + + scp_c1: scp@a0000 { + compatible = "mediatek,scp-core"; + reg = <0xa0000 0x20000>; + reg-names = "sram"; + interrupts = ; + status = "disabled"; + }; }; scp_adsp: clock-controller@10720000 { @@ -2374,7 +2390,7 @@ video-codec@18000000 { compatible = "mediatek,mt8195-vcodec-dec"; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; #address-cells = <2>; #size-cells = <2>; @@ -2540,7 +2556,7 @@ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; interrupts = ; - mediatek,scp = <&scp>; + mediatek,scp = <&scp_c0>; clocks = <&vencsys CLK_VENC_VENC>; clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC>;