From patchwork Mon Jul 10 10:17:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jayesh Choudhary X-Patchwork-Id: 701315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E209EB64DC for ; Mon, 10 Jul 2023 10:17:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233194AbjGJKRj (ORCPT ); Mon, 10 Jul 2023 06:17:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232646AbjGJKR2 (ORCPT ); Mon, 10 Jul 2023 06:17:28 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 497FEDF; Mon, 10 Jul 2023 03:17:20 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 36AAHE5k004719; Mon, 10 Jul 2023 05:17:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1688984234; bh=MwLY4FBHi9lZTqhGGWEYN1L3bveRNx5QeSEeGu+BoL0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DSWWvGmaCluTd1XN0cY3HtTVJ27q2fwXNfvgtUUWOem8XwiFnK1l0Bqon7BTXRqIQ FnpCATrGh5IfRP8oB8molah9lvBxxK+u25pab13B/FWqAhYZevhUiJsGp7KGKraAjI CJTovnf3FdMV1FIak73kVlaI5JGpCu+98sueuGlc= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36AAHDQQ007515 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Jul 2023 05:17:14 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 10 Jul 2023 05:17:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 10 Jul 2023 05:17:13 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36AAHCEi038717; Mon, 10 Jul 2023 05:17:13 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , Subject: [PATCH v5 5/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Date: Mon, 10 Jul 2023 15:47:05 +0530 Message-ID: <20230710101705.154119-6-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230710101705.154119-1-j-choudhary@ti.com> References: <20230710101705.154119-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Rahul T R Enable display for J784S4 EVM. Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for DP HPD. Add the clock frequency for serdes_refclk. Add the endpoint nodes to describe connection from: DSS => MHDP => DisplayPort connector. Also add the GPIO expander-4 node and pinmux for main_i2c4 which is required for controlling DP power. Set status for all required nodes for DP-0 as "okay". Signed-off-by: Rahul T R [j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM] Signed-off-by: Jayesh Choudhary --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 116 +++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 32a3c88cdda5..1678dfc5523b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 { states = <1800000 0x0>, <3300000 0x1>; }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -310,6 +332,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; }; &wkup_pmx2 { @@ -875,3 +910,84 @@ &main_cpsw1_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&main_phy0>; }; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&dss { + status = "okay"; + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; + +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +};