From patchwork Thu Jul 13 11:39:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 702398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D571AC04FE0 for ; Thu, 13 Jul 2023 11:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233181AbjGMLjh convert rfc822-to-8bit (ORCPT ); Thu, 13 Jul 2023 07:39:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234264AbjGMLjN (ORCPT ); Thu, 13 Jul 2023 07:39:13 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B34771FDB; Thu, 13 Jul 2023 04:39:11 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 293448322; Thu, 13 Jul 2023 19:39:10 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 13 Jul 2023 19:39:10 +0800 Received: from localhost.localdomain (183.27.98.46) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 13 Jul 2023 19:39:09 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , "Philipp Zabel" , Conor Dooley , "Emil Renner Berthing" CC: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , , Subject: [PATCH v8 8/9] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Date: Thu, 13 Jul 2023 19:39:01 +0800 Message-ID: <20230713113902.56519-9-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230713113902.56519-1-xingyu.wu@starfivetech.com> References: <20230713113902.56519-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.46] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DVP and HDMI TX pixel external fixed clocks and the rates are 74.25MHz and 297MHz. Acked-by: Palmer Dabbelt Reviewed-by: Emil Renner Berthing Reviewed-by: Conor Dooley Signed-off-by: Xingyu Wu --- .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index fa0061eb33a7..de0f40a8be93 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -38,6 +38,10 @@ gpio-restart { }; }; +&dvp_clk { + clock-frequency = <74250000>; +}; + &gmac0_rgmii_rxin { clock-frequency = <125000000>; }; @@ -54,6 +58,10 @@ &gmac1_rmii_refin { clock-frequency = <50000000>; }; +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + &i2srx_bclk_ext { clock-frequency = <12288000>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ec2e70011a73..e9c1e4ad71a2 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -197,6 +197,12 @@ opp-1500000000 { }; }; + dvp_clk: dvp-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; @@ -221,6 +227,12 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { #clock-cells = <0>; }; + hdmitx0_pixelclk: hdmitx0-pixel-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible = "fixed-clock"; clock-output-names = "i2srx_bclk_ext";