From patchwork Sun Jul 23 16:10:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 705643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5225CC001DE for ; Sun, 23 Jul 2023 16:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229572AbjGWQXP (ORCPT ); Sun, 23 Jul 2023 12:23:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjGWQXM (ORCPT ); Sun, 23 Jul 2023 12:23:12 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DBDD10C2; Sun, 23 Jul 2023 09:22:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0966A60E05; Sun, 23 Jul 2023 16:22:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CF1BC433C8; Sun, 23 Jul 2023 16:22:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690129362; bh=77r49RSSQhAozO3HusyMgOJivNEdF2Oycm6v24MDK60=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LbJaNcSBqDv3TqTL9DOpOFtVQAvmOZDNAcpGCIvWPiAC2ss+7LaTuU60MqlD3oTgS 9zdjwsNlMnz6VUppT+/I9iJyH5BjziWnzaae2/gm//cQwmkfhqPnjGNY7KcPEq2+ZS rgWhVRJaUs/QPnBKydu23WlOGcwokmagkMVqM/4YxcDEXm1irn67kRre/lpUYbbLSk tSJxCz/v6imyZGVT0Hn2/ZJYVroskvzK3TxOwHQT7M8l/+t1+OW/hdKSeDmDRpgby0 9HcL5rXrCzFT7VhH8g3m9QOQco33FQC+fw+ReDl5VuxORDQg2D3IIj1REb9QY6L4v5 SnGealjZlXjLQ== From: Jisheng Zhang To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next 09/10] dt-bindings: net: snps, dwmac: add per channel irq support Date: Mon, 24 Jul 2023 00:10:28 +0800 Message-Id: <20230723161029.1345-10-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230723161029.1345-1-jszhang@kernel.org> References: <20230723161029.1345-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IP supports per channel interrupt, add support for this usage case. Signed-off-by: Jisheng Zhang --- .../devicetree/bindings/net/snps,dwmac.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index bb80ca205d26..525210c2c06c 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -101,6 +101,11 @@ properties: minItems: 1 maxItems: 2 + snps,per-channel-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicates that Rx and Tx complete will generate a unique interrupt for each channel + interrupts: minItems: 1 items: @@ -109,6 +114,8 @@ properties: - description: The interrupt that occurs when Rx exits the LPI state - description: The interrupt that occurs when Safety Feature Correctible Errors happen - description: The interrupt that occurs when Safety Feature Uncorrectible Errors happen + - description: All of the rx per-channel interrupts + - description: All of the tx per-channel interrupts interrupt-names: minItems: 1 @@ -118,6 +125,22 @@ properties: - const: eth_lpi - const: sfty_ce_irq - const: sfty_ue_irq + - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: tx0 + - const: tx1 + - const: tx2 + - const: tx3 + - const: tx4 + - const: tx5 + - const: tx6 + - const: tx7 clocks: minItems: 1