From patchwork Thu Aug 17 16:57:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 714463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74CD3C3DA65 for ; Thu, 17 Aug 2023 17:10:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353779AbjHQRJ6 (ORCPT ); Thu, 17 Aug 2023 13:09:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353891AbjHQRJu (ORCPT ); Thu, 17 Aug 2023 13:09:50 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 884C030D4; Thu, 17 Aug 2023 10:09:44 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1E1C1621A5; Thu, 17 Aug 2023 17:09:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2106C433CD; Thu, 17 Aug 2023 17:09:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692292183; bh=txwgc7mnnsmcD2eGCJ5tky3C5uEWpaD5DMyct9tbf5w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KGFOMjSyshRYy3S7XmxI5nPwYr+UR97M+Uh9kYY13NwiaS+05J/F2VA8eBRBJ+h4g NwVxLm2D4MtYAqWJgx0cxNBFZ+XmiIyaMJKnKfxwYQBmkgCrWo1pVgkmAVjjeaNs7I f8+/jGpS8e+4JeAt6WdDPZ93j2ckQIcov4iPDj1KhSYQgRSWrNc1LdQwRlO+HBP0n2 4wg1UdU4Ue4cpSGbnhMZZ21Sikktib0l3Hfsl7itDJZkueJfK6AgcAoVYSBnYPO8pf Ku6lmXDAQi17J6N1E2v6F3BWBCvKninvj6L6lseyqsi8w37BH3ZBebKR9xKhkpyH7x xF0FHfQHOK8jw== From: Jisheng Zhang To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v5 3/9] net: stmmac: enlarge max rx/tx queues and channels to 16 Date: Fri, 18 Aug 2023 00:57:43 +0800 Message-Id: <20230817165749.672-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230817165749.672-1-jszhang@kernel.org> References: <20230817165749.672-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org xgmac supports up to 16 rx/tx queues and up to 16 channels. Signed-off-by: Jisheng Zhang Acked-by: Alexandre TORGUE --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 5 ++--- include/linux/stmmac.h | 6 +++--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 38782662ff98..8ac994553bc1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -232,9 +232,8 @@ static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue, void __iomem *ioaddr = hw->pcsr; u32 value, reg; - reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1; - if (queue >= 4) - queue -= 4; + reg = XGMAC_MTL_RXQ_DMA_MAP0 + (queue & ~0x3); + queue &= 0x3; value = readl(ioaddr + reg); value &= ~XGMAC_QxMDMACH(queue); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 784277d666eb..9c90e2e295d4 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -15,9 +15,9 @@ #include #include -#define MTL_MAX_RX_QUEUES 8 -#define MTL_MAX_TX_QUEUES 8 -#define STMMAC_CH_MAX 8 +#define MTL_MAX_RX_QUEUES 16 +#define MTL_MAX_TX_QUEUES 16 +#define STMMAC_CH_MAX 16 #define STMMAC_RX_COE_NONE 0 #define STMMAC_RX_COE_TYPE1 1