From patchwork Mon Jan 15 13:20:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 763456 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E378D1756B; Mon, 15 Jan 2024 13:22:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="m3h6QyaJ" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40FD3aHp019271; Mon, 15 Jan 2024 14:21:35 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=m89ZpT5hInkxJ6kBUhZi2kYPPH9r2dSvkVWL2FY78RU=; b=m3 h6QyaJ2TTUmT+AlFe3RK3P7v0+OVDaGRXX1J0TCD9X5FTDNDTUuPBzdberpv3zCS w8IX5+g81WNJu1TeLx3k6SJo/28bE7RxCP0zVPMtMs34b63Q6T8mUwDcD+dhEpUx NDWSrGuZrV5gki1brza2QW9TnS/n2QMEv6coF2M4w2y4OQpRMugnLBfolQo526Ij pjn4NYKccrCe7IaWRCZbqtGmEZO1BlTDYpLYX7DiL4v2zifUEaJXBA+BlQbR6ezw ICkAcGEeBBjTDg5AHQzyuL8+Vr0k3f+/VF0v9Hi2G5c/jQJGPPtQOaUMmGjgRO0A 31mA/oh3HG0ZSrFcGi7Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3vkmfy8st4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jan 2024 14:21:35 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4EF3C10002A; Mon, 15 Jan 2024 14:21:35 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 457732831A8; Mon, 15 Jan 2024 14:21:35 +0100 (CET) Received: from localhost (10.129.178.37) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 15 Jan 2024 14:21:33 +0100 From: Raphael Gallais-Pou To: Yannick Fertre , Raphael Gallais-Pou , Philippe Cornu , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel CC: , , , , Subject: [PATCH v3 4/6] arm64: dts: st: add ltdc support on stm32mp251 Date: Mon, 15 Jan 2024 14:20:07 +0100 Message-ID: <20240115132009.101718-5-raphael.gallais-pou@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240115132009.101718-1-raphael.gallais-pou@foss.st.com> References: <20240115132009.101718-1-raphael.gallais-pou@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5189d5a4f6a9..4446996c8f5d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -218,6 +218,18 @@ i2c8: i2c@46040000 { status = "disabled"; }; + ltdc: display-controller@48010000 { + compatible = "st,stm32-ltdc"; + reg = <0x48010000 0x400>; + st,syscon = <&syscfg>; + interrupts = , + ; + clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + clock-names = "bus", "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + }; + sdmmc1: mmc@48220000 { compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00353180>;