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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id fm16-20020a05600c0c1000b0040ea10178f3sm77470wmb.21.2024.01.19.02.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 02:45:45 -0800 (PST) From: Tudor Ambarus To: gregkh@linuxfoundation.org, jirislaby@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, peter.griffin@linaro.org, semen.protsenko@linaro.org, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 18/19] tty: serial: samsung: change has_divslot type to bool Date: Fri, 19 Jan 2024 10:45:25 +0000 Message-ID: <20240119104526.1221243-19-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240119104526.1221243-1-tudor.ambarus@linaro.org> References: <20240119104526.1221243-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since the driver was introduced the port features flags never extended. As we don't expect more flags soon that would bypass the first cacheline of ``struct s3c24xx_uart_info``, change the type of ``has_divslot`` to bool. Bitfields operations incur performance penalty when set or read as compared to direct types. Signed-off-by: Tudor Ambarus --- drivers/tty/serial/samsung_tty.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index c429029c0207..0a03df44211d 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -89,8 +89,7 @@ struct s3c24xx_uart_info { u8 iotype; /* uart port features */ - - unsigned int has_divslot:1; + bool has_divslot; }; struct s3c24xx_serial_drv_data { @@ -2400,7 +2399,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { .port_type = PORT_S3C6400, .iotype = UPIO_MEM, .fifosize = 64, - .has_divslot = 1, + .has_divslot = true, .rx_fifomask = S3C2440_UFSTAT_RXMASK, .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, .rx_fifofull = S3C2440_UFSTAT_RXFULL, @@ -2429,7 +2428,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .type = TYPE_S3C6400, .port_type = PORT_S3C6400, .iotype = UPIO_MEM, - .has_divslot = 1, + .has_divslot = true, .rx_fifomask = S5PV210_UFSTAT_RXMASK, .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, .rx_fifofull = S5PV210_UFSTAT_RXFULL, @@ -2459,7 +2458,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .type = TYPE_S3C6400, \ .port_type = PORT_S3C6400, \ .iotype = UPIO_MEM, \ - .has_divslot = 1, \ + .has_divslot = true, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ @@ -2498,7 +2497,7 @@ static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = { .type = TYPE_S3C6400, .port_type = PORT_S3C6400, .iotype = UPIO_MEM32, - .has_divslot = 1, + .has_divslot = true, .rx_fifomask = S5PV210_UFSTAT_RXMASK, .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, .rx_fifofull = S5PV210_UFSTAT_RXFULL, @@ -2569,7 +2568,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = { .port_type = PORT_S3C6400, .iotype = UPIO_MEM, .fifosize = 64, - .has_divslot = 1, + .has_divslot = true, .rx_fifomask = S5PV210_UFSTAT_RXMASK, .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, .rx_fifofull = S5PV210_UFSTAT_RXFULL,