From patchwork Mon Jan 29 13:27:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 767704 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66B4634F8; Mon, 29 Jan 2024 13:27:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534881; cv=none; b=UNw5Z7NslysRNjY53quXm4wadeHN8iVrEQfmk9+JRdWAwSf5UQUGqtYbOJGF10YabUa7WDaWE/2wOCwUEz/vTHagQoKNAVt//Qdw+4YBy+Pl5bCNf94opCJNcmliSFBtlS0Y2+SOTa5f6RiXR707BZrh3Nz3CjbF3btcf0JWK2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534881; c=relaxed/simple; bh=vducFJeFkLdtwA38Jvbd3L1iibUB5ilE2u9MWdmjSoI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l21PQMxuW4p4a14xeckS6EfbYgHVtL5nPm/4nVbqieDnYfKruZvGkNQzXYDtOlAxDNdWg1Qd35zm1JJuwxeaVQI89SmUw8ty2FBoDaWBr3Hfqk7C48DK0DFYQjWiGTMbP+hkp4X1Jh/bEJSwYZ/yzITGg9wmfcooNBwwNpw6iME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=NFllUqx9; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NFllUqx9" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRpsS128833; Mon, 29 Jan 2024 07:27:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706534871; bh=/ql4DV3w2pKY7iVs419kuEdwMG95w7SUYZxvgOJ1+5I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NFllUqx9BtkI/F6/OPo9P2N7k/ymTtHQfzu+mQFHTy8dQsEQEdhT3z0/O49uWU1y6 4RICnI0JXitvCiApIn9pPqQv1PjKQywSxKhM//paCViP3AsmffF++1W4P63OCSyuXq ykGop3digGs8VYSSV1LUpj2EFI8HapDlAPtvFO9A= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40TDRp4T030321 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jan 2024 07:27:51 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 07:27:50 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 07:27:50 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9B036720; Mon, 29 Jan 2024 07:27:47 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Mon, 29 Jan 2024 18:57:34 +0530 Message-ID: <20240129132742.1189783-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Signed-off-by: Vaishnav Achath --- .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c6b85bbf9a17..3667aa179306 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay";