From patchwork Tue Jul 13 06:28:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 477056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D38D8C11F6D for ; Tue, 13 Jul 2021 06:28:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AAEC46128C for ; Tue, 13 Jul 2021 06:28:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234159AbhGMGbh (ORCPT ); Tue, 13 Jul 2021 02:31:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:51122 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233934AbhGMGbf (ORCPT ); Tue, 13 Jul 2021 02:31:35 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 33E7F61284; Tue, 13 Jul 2021 06:28:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626157725; bh=beQ/nlrqcVJKSEttIL89uLGSbQ5pFqjunHiG0KZXdfc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mtUJl1n8wkfbz1Lr0Fb1MinklwzlNDMTbayd5c5bx/82H5Ipo9p0xAjOtUvKorane gR3+5eOLCmkB2XMcUVUgVwswWPIOK/UgRx8PUzvdHZY4SWEnlZIOxgv0qC1Vzb3keW TCQItGa20dTj50WM64jJNtPDksLNLJURYW7ZItZke04YDwKlpinc15/1hV+SDuk/I8 KF/ZuGGgzVV/9waOpbIYNgKxp6mOJmnFH6e4rA0ssNNY8dYkDQzCLRShtIvd70Uvip cb1dwjWuzw76LgOcj8zl9cMdrkKTUzjFrkvIdSbUvwISiCvR41CS0zFAdoqKeAL3hZ FAeLJv49hbnlg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m3BuM-005yPX-QG; Tue, 13 Jul 2021 08:28:42 +0200 From: Mauro Carvalho Chehab To: Bjorn Helgaas Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , "Manivannan Sadhasivam" , "Rob Herring" , Kishon Vijay Abraham I , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 1/8] dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY Date: Tue, 13 Jul 2021 08:28:34 +0200 Message-Id: <390e7fc0cd6fa4217f5d67c74f12ea101fab3f6d.1626157454.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for HiKey 960 (hi3660) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3660-pcie.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml new file mode 100644 index 000000000000..81c93e76cef4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin960 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 960. + +properties: + compatible: + const: hisilicon,hi960-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_aux + - const: pcie_apb_phy + - const: pcie_apb_sys + - const: pcie_aclk + + reset-gpios: + description: PCI PERST reset GPIO + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + }; +...