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[23.128.96.18]) by mx.google.com with ESMTP id u2si3366218edy.251.2020.09.10.03.01.06; Thu, 10 Sep 2020 03:01:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Edlxp9JS; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730400AbgIJKBE (ORCPT + 6 others); Thu, 10 Sep 2020 06:01:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730500AbgIJJzr (ORCPT ); Thu, 10 Sep 2020 05:55:47 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B851C061573 for ; Thu, 10 Sep 2020 02:55:47 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id u9so660750plk.4 for ; Thu, 10 Sep 2020 02:55:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IaGTFnDJBMBefRV/KyfCTUkPl/xUCziFjmJJ4w4CjXw=; b=Edlxp9JSKyIwQ3d/65GRMff66HrC1LW3hK1xF7+fYi4S6Ae7V+W1mIakpvOTcZon4U uKl4ve/gMbyjqYC5YhLJXnXlJlPCtCu7YZDE0yKdmiBUnG/ZlxdUXJkg596ZDVjZwwhe bh1seKT7/YWFj3gVY1RAzKdf1BvZPtlp5fuylziTmuSW7fJ0uqXqO0Hl9rYrYZhzt6vK lAnwIFGqCsHGlHUHQSWZ++lQAX0n7wKlwA5octgAgeiMFwjkAnfwvmLXDjpsLbFj6YQb BHICuApDFIBstBzxunt/ssewC+a8+qyGh0mam78c+TCYgHB+iRq57dCkJAQL2qOzYCLR FlzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IaGTFnDJBMBefRV/KyfCTUkPl/xUCziFjmJJ4w4CjXw=; b=akjdyJ0NPyvjDbO5CBaePzNl43l5nQ4Uvme7PtsPLBLywpAzkK6sNpgimb+18yPDL1 edT+GOpznokMiPlJNRQlzGzqDg6YW8sR4HgNKiWUFphr7/5Sl02K1l6r2c7KnbExWiBi 1TIQCn+e5dB5ae3x+PAHFUDhAW28LdMkJNWNZiL8N5pIBqDfdKMty2stSe7u3fQ1nBgR ajIvmWG/gfhcd70SqtaXjvdGUGjvynW0JbQicn9pJFnZ/66T011s/KoF4I+OlJX827t6 RQcgyiW9JN3dLs9bHvkx7tAjFeNsAIoDxCeTSsqElUkzWy2eKdDnpNQjopoWeEfparTj u7vg== X-Gm-Message-State: AOAM530QnGRQ9+Hf75I7yUrNLJ9QL3OA7fWZPvCGM68S8eaIr8La8hk4 Fczgd75l7QCTX8iQkrUxh7XhoQ== X-Received: by 2002:a17:90b:3105:: with SMTP id gc5mr4616714pjb.225.1599731746660; Thu, 10 Sep 2020 02:55:46 -0700 (PDT) Received: from localhost ([122.181.54.133]) by smtp.gmail.com with ESMTPSA id s3sm5385018pfe.116.2020.09.10.02.55.45 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 10 Sep 2020 02:55:46 -0700 (PDT) From: Viresh Kumar To: Rob Herring , Jassi Brar , Jassi Brar Cc: Viresh Kumar , Vincent Guittot , Arnd Bergmann , Frank Rowand , Bjorn Andersson , linux-arm-kernel@lists.infradead.org, Sudeep Holla , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/2] dt-bindings: mailbox: add doorbell support to ARM MHU Date: Thu, 10 Sep 2020 15:25:19 +0530 Message-Id: <5d448f579a41345130ae25d01bb94a6e293a6460.1599731645.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.25.0.rc1.19.g042ed3e048af In-Reply-To: <7f50b23d157a97242c79bd8f2ab649a9272b9b59.1599731645.git.viresh.kumar@linaro.org> References: <7f50b23d157a97242c79bd8f2ab649a9272b9b59.1599731645.git.viresh.kumar@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sudeep Holla The ARM MHU's reference manual states following: "The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt." This patch thus extends the MHU controller's DT binding to add support for doorbell mode. Though the same MHU hardware controller is used in the two modes, A new compatible string is added here to represent the combination of the MHU hardware and the firmware sitting on the other side (which expects each bit to represent a different signal now). Signed-off-by: Sudeep Holla Co-developed-by: Viresh Kumar Signed-off-by: Viresh Kumar --- V3: Update the json schema and fix number of interrupt lines. .../devicetree/bindings/mailbox/arm,mhu.yaml | 60 +++++++++++++++++-- 1 file changed, 54 insertions(+), 6 deletions(-) -- 2.25.0.rc1.19.g042ed3e048af Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index 4e840cedb2e4..88980ba005a4 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -18,20 +18,40 @@ description: | remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. + The MHU hardware also allows operations in doorbell mode. The MHU drives the + interrupt signal using a 32-bit register, with all 32-bits logically ORed + together. It provides a set of registers to enable software to set, clear and + check the status of each of the bits of this register independently. The use + of 32 bits per interrupt line enables software to provide more information + about the source of the interrupt. For example, each bit of the register can + be associated with a type of event that can contribute to raising the + interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote + processor. + # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: - const: arm,mhu + enum: + - arm,mhu + - arm,mhu-doorbell required: - compatible properties: compatible: - items: - - const: arm,mhu - - const: arm,primecell + oneOf: + - description: Data transfer mode + items: + - const: arm,mhu + - const: arm,primecell + + - description: Doorbell mode + items: + - const: arm,mhu-doorbell + - const: arm,primecell + reg: maxItems: 1 @@ -50,8 +70,11 @@ description: | - const: apb_pclk '#mbox-cells': - description: Index of the channel. - const: 1 + description: | + Set to 1 in data transfer mode and represents index of the channel. + Set to 2 in doorbell mode and represents index of the channel and doorbell + number. + enum: [ 1, 2 ] required: - compatible @@ -62,6 +85,7 @@ description: | additionalProperties: false examples: + # Data transfer mode. - | soc { #address-cells = <2>; @@ -84,3 +108,27 @@ additionalProperties: false mboxes = <&mhuA 1>; /* HP-NonSecure */ }; }; + + # Doorbell mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scpi: scpi@2f000000 { + compatible = "arm,scpi"; + reg = <0 0x2f000000 0 0x200>; + mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + }; + };