From patchwork Sun Dec 1 13:49:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyri Sarha X-Patchwork-Id: 180538 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp4013478ile; Sun, 1 Dec 2019 05:49:47 -0800 (PST) X-Google-Smtp-Source: APXvYqw0scrxuowF3iBPKN5qs/SLH20l9f2t2+TGkIy7lXcCPlsFPAFcq6rOfRBOkI3O3M09lt1i X-Received: by 2002:a17:906:4e96:: with SMTP id v22mr46183037eju.219.1575208187518; Sun, 01 Dec 2019 05:49:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575208187; cv=none; d=google.com; s=arc-20160816; b=tfltGk0MsQjwBrMj4XOckH/Ji3vGz+r+Wg17ufeNy5BxVlqh1VIaYo/qnGeWFepR5D Wdzf3G3YP5XoLxGTz/6zrqb3OY8rUDq2PzleOfOgjj3dShAa5+EH4nxH7pdwUyaRlIod mkbp+3/9W5TuUPuvezqsZExPjTQsf11NUqpw8C9bDzTeajwgcwtCfyQ9gQuaxQrLYNp3 tCm61/H5aCIb59kV5+FEMxyvI5Q10Vs3AKxA3mEOHfdgjgZg9WFBLZcWp5THL5ugXX7H QQpdYTGovVvoZQnoDqUwkCnLiJJkO+bEkDpjHqYT/KxmX5OPUAP4HwyU7SIFuIJtsPbM ejJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=pUi7eFA5fQV+ZfC8P4wsmQMB0SvMAESj7mgDXEnyv5M=; b=QIWudYzHRx5QKto/9yu01VBXTRn++yEZKAW5H6kAtldesxiN+n9P4QWFbT7izx/03X yp/qwhh8zbWVlEj8ewBdsJ769gG6Ebr0Dwa3pO/KoYhOmjPIBGGgSXYxKkfvKRfgkl0h PAzng6ofEYGmRegj4SNBfkbSGffXmjCJr6VNwIB/83FbFdDC0plYYw9eWNWW5fbF4J6q 28i7DFLz2vLYsMaFZ1zENGS+pzdCKDXNjyTh9XOaz1xGm14zOJx3H8xWv/cWBzWbMMHl Wwf5F7B+P9H0ADUQbIJritJE6nKlcbg+Hna43G7DznbPYU5b0QkXpKiRRL+2kbBfeSHT /m/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wh0glziJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y4si12454970eds.288.2019.12.01.05.49.47; Sun, 01 Dec 2019 05:49:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wh0glziJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726489AbfLANto (ORCPT + 8 others); Sun, 1 Dec 2019 08:49:44 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53064 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726340AbfLANto (ORCPT ); Sun, 1 Dec 2019 08:49:44 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB1Dnc2A016265; Sun, 1 Dec 2019 07:49:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575208178; bh=pUi7eFA5fQV+ZfC8P4wsmQMB0SvMAESj7mgDXEnyv5M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wh0glziJTclIRriljhjoS0H6palvx4en8gnRJrpn+FahcktbxeMr+YoM7vgMsrGit UqyBSbeldRDpy/iUvVlDUov2uXeTpUon9vKbhzBkH/rI3EOb1wljgU3M2PyuMZ0/KS TYhSGVORY+lDxGFKMPVf37lfL7lPMG3dJWuqmhLw= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB1Dncda068104 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 1 Dec 2019 07:49:38 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Sun, 1 Dec 2019 07:49:37 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Sun, 1 Dec 2019 07:49:37 -0600 Received: from jadmar.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB1DnW5a111790; Sun, 1 Dec 2019 07:49:35 -0600 From: Jyri Sarha To: , CC: , , , , , , , , Subject: [PATCH v2 2/5] dt-bindings: display: ti, am65x-dss: Add dt-schema yaml binding Date: Sun, 1 Dec 2019 15:49:30 +0200 Message-ID: <625fa000c744300b132d376dedf9b7ad83f6f2da.1575203210.git.jsarha@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt-schema yaml bindig for AM65x DSS, AM65x version TI Keystone Display SubSystem. Signed-off-by: Jyri Sarha --- .../bindings/display/ti/ti,am65x-dss.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml new file mode 100644 index 000000000000..6691f5dad383 --- /dev/null +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments AM65x Display Subsystem + +maintainers: + - Jyri Sarha + - Tomi Valkeinen + +description: | + The AM65x TI Keystone Display SubSystem with two output ports and + two video planes. The first video port supports OLDI and the second + supports DPI format. The fist plane is full video plane with all + features and the second is a "lite plane" without scaling support. + +properties: + compatible: + const: ti,am65x-dss + + reg: + maxItems: 7 + minItems: 7 + + reg-names: + items: + - const: common + - const: vidl1 + - const: vid + - const: ovr1 + - const: ovr2 + - const: vp1 + - const: vp2 + + clocks: + maxItems: 3 + minItems: 3 + + clock-names: + items: + - const: fck + - const: vp1 + - const: vp2 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + description: phandle to the associated power domain + + port@0: + type: object + description: + The DSS OLDI output port node form video port 1 + + port@1: + type: object + description: + The DSS DPI output port node from video port 2 + + ti,am65x-oldi-io-ctrl: + maxItems: 1 + description: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + phandle to syscon device node mapping OLDI IO_CTRL registers. + The mapped range should point to OLDI_DAT0_IO_CTRL, map it and + following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL, + and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI + interface to work. + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input memory (from main memory to dispc) bandwidth limit in + bytes per second + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + dss: dss@04a00000 { + compatible = "ti,am65x-dss"; + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ + <0x0 0x04a06000 0x0 0x1000>, /* vid */ + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; + clock-names = "fck", "vp1", "vp2"; + + interrupts = ; + + status = "disabled"; + + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; + };