From patchwork Tue Feb 11 03:21:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 204948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AB29C3B186 for ; Tue, 11 Feb 2020 03:22:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4634A20661 for ; Tue, 11 Feb 2020 03:22:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="loIBcNZY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728055AbgBKDWI (ORCPT ); Mon, 10 Feb 2020 22:22:08 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:5959 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728009AbgBKDWH (ORCPT ); Mon, 10 Feb 2020 22:22:07 -0500 X-UUID: 7d3ccdbd7a984608945e406a38d1187f-20200211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=OZPXyaPUwF7OiceDOOHUCK3pwRAfAn9mY3k+hvqHy2U=; b=loIBcNZYCNrs53ph1R7jqZ2qo12o1p3TgyYQBvbm2EvF2CyoVyQTF1EDc+TpfHFRhuF8toGW9jL21Wq61UVbx1Up093DzjUYZmSNZzrPrShcNMYFOtvTBt+2PSV1SJ7vCVz8QQwzxGCCJy6wc4mGWcCKIrJtnq2iKR/Xtuh8EqM=; X-UUID: 7d3ccdbd7a984608945e406a38d1187f-20200211 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1964896838; Tue, 11 Feb 2020 11:21:55 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 11 Feb 2020 11:20:08 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 11 Feb 2020 11:20:59 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Rob Herring , Mark Rutland , Matthias Brugger , , Chunfeng Yun , , , Subject: [RESEND PATCH v5 06/11] phy: phy-mtk-tphy: add a property for disconnect threshold Date: Tue, 11 Feb 2020 11:21:11 +0800 Message-ID: <6de44061814ec3633933af2003878f6418148cfe.1581389234.git.chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: References: MIME-Version: 1.0 X-TM-SNTS-SMTP: CB15E578AF22B411B60D4ECD7DEB9D1265F937E1BDAA991A742CEF019AE963902000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by: Chunfeng Yun --- v5: no changes v4: change commit log v2~3: no changes --- drivers/phy/mediatek/phy-mtk-tphy.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.25.0 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index cb2ed3b25068..5afe33621dbc 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -60,6 +60,8 @@ #define U3P_USBPHYACR6 0x018 #define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) +#define PA6_RG_U2_DISCTH GENMASK(7, 4) +#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH GENMASK(3, 0) #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) @@ -300,6 +302,7 @@ struct mtk_phy_instance { int eye_src; int eye_vrt; int eye_term; + int discth; bool bc12_en; }; @@ -850,9 +853,12 @@ static void phy_parse_property(struct mtk_tphy *tphy, &instance->eye_vrt); device_property_read_u32(dev, "mediatek,eye-term", &instance->eye_term); - dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d\n", + device_property_read_u32(dev, "mediatek,discth", + &instance->discth); + dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, disc:%d\n", instance->bc12_en, instance->eye_src, - instance->eye_vrt, instance->eye_term); + instance->eye_vrt, instance->eye_term, + instance->discth); } static void u2_phy_props_set(struct mtk_tphy *tphy, @@ -888,6 +894,13 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); writel(tmp, com + U3P_USBPHYACR1); } + + if (instance->discth) { + tmp = readl(com + U3P_USBPHYACR6); + tmp &= ~PA6_RG_U2_DISCTH; + tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth); + writel(tmp, com + U3P_USBPHYACR6); + } } static int mtk_phy_init(struct phy *phy)