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[209.132.180.67]) by mx.google.com with ESMTP id d62si1534791pfc.104.2019.03.29.03.12.36; Fri, 29 Mar 2019 03:12:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ey4hlv9N; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728828AbfC2KMg (ORCPT + 7 others); Fri, 29 Mar 2019 06:12:36 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:37715 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728793AbfC2KMg (ORCPT ); Fri, 29 Mar 2019 06:12:36 -0400 Received: by mail-wr1-f65.google.com with SMTP id w10so1866768wrm.4 for ; Fri, 29 Mar 2019 03:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=+TYtSQVH2QGKxuvpbRnS7W6hHgOIHYvxh6y+HNRyviU=; b=Ey4hlv9NkuLcAMge47eh2MgZLE/ZAhUcJW3vteVwHV9CdE/I3Fn8mh2zYtUxUh/jn7 lsNANyD/GLLLsGjgBKeTHR4AhZxK1s2OO8+L++84vvmN1xvJPkJ9/dYXjmx9qDccsDvZ X3zQQHf0EPOBRP6hfJxGYc48/usdTnc9AyHO32engsqayS+/yJv7Yy2RYaBF8lQr5ZHS Tm8dKV85wfToe+JUgl+BUTO7ufj2i/8FrC2vWzvO6nesj7DMgRg1uXxwuXpcUO9ufRWo xVdp2ihtNb1LF+GYLGT1FBtlohypH6HuHbaY9o5b0cklgheOMfGV/NiH3B9sa3XOHF5r GIZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=+TYtSQVH2QGKxuvpbRnS7W6hHgOIHYvxh6y+HNRyviU=; b=P8YBXBpcoR+3Yf974lg/qcYUR7WcEDs40+CZPR3T/wd4EXpuWgAygdzXUIFfvyrdNk V4LnKOlqPSskOG/kgQBggWtFeIvN23dQ+pBZOqhszSKk0j5p3F3vDeECGxKrcPq/fyk1 /IGgE+8naQAupmJ5m8ukS1Y3o8utwoEuE3zLCDFvsfpQISxjEc920FbFBttSZ1DBozPZ qgV/cu8pkQU9xqKaTAfYqDWL+DO+AcoqToR0cqFj7dRIaPpKDkN/q8pruLZcJQhH7wgS h2xN0//h7isACgNotyjs7E7pHt0v8UggESnXQbIJB00ajlaytxDgLdXXoqLrykEANnzr ZFeA== X-Gm-Message-State: APjAAAUu53My3DNnWxJSrKaUMAPe8AECLKNn/mJ2IY/5FSYivo4x57Yo 4akX+CYFx7RRXVOfAxqS3ukBRcPOdg0= X-Received: by 2002:adf:ec11:: with SMTP id x17mr29398866wrn.120.1553854354201; Fri, 29 Mar 2019 03:12:34 -0700 (PDT) Received: from localhost ([49.248.196.175]) by smtp.gmail.com with ESMTPSA id l12sm1912888wrt.31.2019.03.29.03.12.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 29 Mar 2019 03:12:33 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, David Brown Cc: devicetree@vger.kernel.org Subject: [PATCH v2 01/13] arm64: dts: msm8998: thermal: split address space into two Date: Fri, 29 Mar 2019 15:42:07 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8998 that has a similar register layout. The order is important (TM before SROT) because we make an assumption that SROT is always the second address space in order to support legacy DTs. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3fd0769fe648..ac25e9142cbd 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -590,17 +590,19 @@ cell-index = <0>; }; - tsens0: thermal@10aa000 { + tsens0: thermal@10ab000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x10aa000 0x2000>; + reg = <0x10ab000 0x1000>, /* TM */ + <0x10aa000 0x1000>; /* SROT */ #qcom,sensors = <12>; #thermal-sensor-cells = <1>; }; - tsens1: thermal@10ad000 { + tsens1: thermal@10ae000 { compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x10ad000 0x2000>; + reg = <0x10ae000 0x1000>, /* TM */ + <0x10ad000 0x1000>; /* SROT */ #qcom,sensors = <8>; #thermal-sensor-cells = <1>;