From patchwork Mon Sep 21 15:41:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 254211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75C59C43468 for ; Mon, 21 Sep 2020 15:41:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3071820C09 for ; Mon, 21 Sep 2020 15:41:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600702884; bh=RY94d6pIIDZW47GNN0JTfYPkHaxh9ahah25E+nfPXHI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=iqPAM/4tpAuRpEcdXX0NPFBRmddDjwlPjbxDqw5+DkthSsiCf50DdLT1BxNhIWfY2 2lyySpJwfdZGWrtGZdBUt135uJxgRb18c4vWVZCW0NWlJPjpizPcJrrbw6ELfYkr44 XadpzKuOMfelw4P0j4kZJ4dRoYJtEKzuZuhEoO+4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727303AbgIUPlY (ORCPT ); Mon, 21 Sep 2020 11:41:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:54772 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726690AbgIUPlX (ORCPT ); Mon, 21 Sep 2020 11:41:23 -0400 Received: from e123331-lin.nice.arm.com (lfbn-nic-1-188-42.w2-15.abo.wanadoo.fr [2.15.37.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CA0E220B1F; Mon, 21 Sep 2020 15:41:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600702883; bh=RY94d6pIIDZW47GNN0JTfYPkHaxh9ahah25E+nfPXHI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RbDSY98qFnusIRwcoPCsHf3xJ4h1dOYyzdlmlfdxIPFEY2rGlmk3QmWxTt8eRTZ2m bWVqD11jTaqv4fFnV0klEYFRyIPamoEIZE/mtcRlHvfKIYVbFKb4Kt+U/S5xQcOgAS 0AuyV5sLNnXv+kMImlU97u0sNn3mxpITXSUDpLAc= From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-efi@vger.kernel.org, Ard Biesheuvel , Zhen Lei , Russell King , Linus Walleij , Nicolas Pitre Subject: [PATCH v2 01/10] ARM: p2v: fix handling of LPAE translation in BE mode Date: Mon, 21 Sep 2020 17:41:08 +0200 Message-Id: <20200921154117.757-2-ardb@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200921154117.757-1-ardb@kernel.org> References: <20200921154117.757-1-ardb@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org When running in BE mode on LPAE hardware with a PA-to-VA translation that exceeds 4 GB, we patch bits 39:32 of the offset into the wrong byte of the opcode. So fix that, by rotating the offset in r0 to the right by 8 bits, which will put the 8-bit immediate in bits 31:24. Note that this will also move bit #22 in its correct place when applying the rotation to the constant #0x400000. Signed-off-by: Ard Biesheuvel Reviewed-by: Linus Walleij --- arch/arm/kernel/head.S | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f8904227e7fd..98c1e68bdfcb 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -671,12 +671,8 @@ ARM_BE8(rev16 ip, ip) ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b bx lr -#else -#ifdef CONFIG_CPU_ENDIAN_BE8 - moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction #else moveq r0, #0x400000 @ set bit 22, mov to mvn instruction -#endif b 2f 1: ldr ip, [r7, r3] #ifdef CONFIG_CPU_ENDIAN_BE8 @@ -685,7 +681,7 @@ ARM_BE8(rev16 ip, ip) tst ip, #0x000f0000 @ check the rotation field orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0 @ mask in offset bits 7-0 + orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 #else bic ip, ip, #0x000000ff tst ip, #0xf00 @ check the rotation field