From patchwork Wed Oct 14 10:07:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 285605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E33FC433DF for ; Wed, 14 Oct 2020 10:07:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C98CE221FE for ; Wed, 14 Oct 2020 10:07:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OfYU6MkC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728917AbgJNKHR (ORCPT ); Wed, 14 Oct 2020 06:07:17 -0400 Received: from esa4.microchip.iphmx.com ([68.232.154.123]:45000 "EHLO esa4.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726435AbgJNKHR (ORCPT ); Wed, 14 Oct 2020 06:07:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1602670037; x=1634206037; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=VGTfgckfg8TV8Weu5D11OdbauQdotcdSuN4L8L+qkB0=; b=OfYU6MkCNm3OwA1v27lto/el6/hD2dt5MkFy5qh7MftEqW64qA/vdVxN ZvLM6DF14QnJOHMJxMKTZMQ/Ce8wzYsptjcWEWatAb+vKiXPygi/+Igb2 fVoxBftvF67lmTrRJMxTrsP7gmRqdElaBMN8IvWByik1eY21BUxmfp1wN W07xuMkn4dTTWtYBCvFuaOXCA11CcHf+p4zZaLt23DvB0Z+v63Ows9KCb x5Y/+BkjP+GNQtN+rnJ2XTyGoHpJjttCoJHz+0DZcmPedUoyUJJkssvK9 msOriVc0dW0sB0G0lHeHT3n/uGXfLlRZ5ezwH9LV2oYYezEcPWeMWoIwa A==; IronPort-SDR: QjCZYNQytIYC1K1BsKSqIhu1hl2rSKz2Fle8Y0Z30kuVodANbWY4wank1ksfbx5ewDB+pRakOY WlMEzRRyuVNl6CKdTYh7mpSkUqzmx3//Tw7w5qi/v7bib9hV8MlQ2qCcZ7SQYZEJVWQKh5jzpH suS82iNU+SIhurwyrColLB0uZla6gV2krJHyGlj0yRtymxPtq+Z6qEwd2d55LtjSIduMMWb6QY WTkxkGh9Rwo1Kvn6AnSniLTnz2BDZikQuVR2qAkeJ0dsitib7eAagVRR+qBuVehPrBspji0h86 lNg= X-IronPort-AV: E=Sophos;i="5.77,374,1596524400"; d="scan'208";a="90132102" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Oct 2020 03:07:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 14 Oct 2020 03:07:15 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 14 Oct 2020 03:07:14 -0700 From: Lars Povlsen To: Linus Walleij CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH v6 0/3] Adding support for Microchip/Microsemi serial GPIO controller Date: Wed, 14 Oct 2020 12:07:04 +0200 Message-ID: <20201014100707.2728637-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The series add support for the serial GPIO controller used by Microchip Sparx5, as well as (MSCC) ocelot/jaguar2 SoCs. v6 changes: - Use "bus-frequency" instead of "microchip,sgpio-frequency". Drop '$ref'. (Robh) - Added "ngpios" description, bumped minimum to 32. (Linus) - Added "#size-cells" description. (Linus) - Changed "bus-frequency" validation in driver to reflect the YAML description. v5 changes (driver comments from Linus): - Collect bank data in sgpio_bank struct - Add is_input boolean to sgpio_bank struct - Use single-bit bitmasks in sgpio_output_set() and sgpio_output_get() - Eliminate superfluous struct pinctrl_dev *pctl_dev in bank data - Fix wrong ngpio consistency check v4 changes (binding comments from Rob): - microchip,sgpio-port-ranges changed to uint32-matrix so tuples can be represented properly. - gpio controller node name changed to "gpio@[0-1]" - whitespace fixes - DT files updated as per schema changes v3 changes: - Renamed all usage of "mchp" abbrevation with "microchip". - Split the in/output directions into (two) separate banks. - Eliminated the bindings include file (from above) - Changed SPDX license to "GPL-2.0-or-later" - Change -ENOTSUPP to -EOPNOTSUPP - Minor type/symbol naming changes v2 changes: - Adds both in and output modes. - Use direct adressing of the individual banks (#gpio-cells = <4>), also osoleting need for addressing macros in bindings include file. - Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by proper range set (array of [start,end]) 'microchip,sgpio-port-ranges'. - Fixes whitespace issues in Kconfig file Lars Povlsen (3): dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO arm64: dts: sparx5: Add SGPIO devices Lars Povlsen (3): dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO arm64: dts: sparx5: Add SGPIO devices .../pinctrl/microchip,sparx5-sgpio.yaml | 145 ++++ MAINTAINERS | 1 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 +++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 + .../dts/microchip/sparx5_pcb134_board.dtsi | 258 +++++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 55 ++ drivers/pinctrl/Kconfig | 18 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-microchip-sgpio.c | 667 ++++++++++++++++++ 9 files changed, 1241 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml create mode 100644 drivers/pinctrl/pinctrl-microchip-sgpio.c --- 2.25.1