| Message ID | 20210803175109.1729-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| Headers | show |
| Series | Renesas RZ/G2L IRQC support | expand |
On Tue, Aug 3, 2021 at 7:51 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > Renesas RZ/G2L SoC's with below pins: > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > maximum of only 32 can be mapped to 32 GIC SPI interrupts, This looks good to me but I count on Geert to do final review, merge and send pull requests for everything Renesas. Yours, Linus Walleij
On Tue, Aug 3, 2021 at 7:51 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > +description: | > + The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts, > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts, > + - NMI edge select. Not that we don't have weird documentation but what on earth is an "NMI edge"??? I know about rising and falling edges, and I know about non-maskable interrupts. But NMI edge? Maybe expand this to explain what it is? Yours, Linus Walleij
On Tue, Aug 03, 2021 at 06:51:06PM +0100, Lad Prabhakar wrote: > Add DT bindings for the Renesas RZ/G2L Interrupt Controller. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../renesas,rzg2l-irqc.yaml | 129 ++++++++++++++++++ > 1 file changed, 129 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > new file mode 100644 > index 000000000000..66d6a0ebe128 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > @@ -0,0 +1,129 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L Interrupt Controller > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > + - Geert Uytterhoeven <geert+renesas@glider.be> > + > +description: | > + The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's missing 'with below pins:"? > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts, > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts, > + - NMI edge select. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-irqc # RZ/G2L > + - const: renesas,rzg2l-irqc > + > + '#interrupt-cells': > + const: 2 > + > + '#address-cells': > + const: 0 > + > + interrupt-controller: true > + > + reg: > + maxItems: 1 > + > + interrupts: > + description: Specifies the GIC interrupts. > + maxItems: 41 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: clk > + - const: pclk > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - '#interrupt-cells' > + - '#address-cells' > + - interrupt-controller > + - reg > + - interrupts > + - clocks > + - clock-names > + - power-domains > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/r9a07g044-cpg.h> > + > + irqc: interrupt-controller@110a0000 { > + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; > + #interrupt-cells = <2>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x110a0000 0x10000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, > + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; > + clock-names = "clk", "pclk"; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G044_IA55_RESETN>; > + }; > -- > 2.17.1 > >
Hi Linus, Thank you for the review. On Wed, Aug 11, 2021 at 1:10 PM Linus Walleij <linus.walleij@linaro.org> wrote: > > On Tue, Aug 3, 2021 at 7:51 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > +description: | > > + The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's > > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts, > > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts, > > + - NMI edge select. > > Not that we don't have weird documentation but what on earth is an > "NMI edge"??? > On this SoC NMI is not treated as an NMI exception, the irqc has bits to select the NMI interrupt (Rising/Falling-edge) detection. > I know about rising and falling edges, and I know about non-maskable > interrupts. But NMI edge? Maybe expand this to explain what it is? > sure will add more details on the above. Cheers, Prabhakar
Hi All, The RZ/G2L Interrupt Controller is a front-end for the GIC found on Renesas RZ/G2L SoC's with below pins: - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a maximum of only 32 can be mapped to 32 GIC SPI interrupts, - NMI edge select. _____________ | GIC | | ________ | ____________ | | | | NMI ------------------------------------>| | SPI0-479 | | GIC-600| | _______ | |------------>| | | | | | | PPI16-31 | | | | | | IRQ0-IRQ8 | IRQC |------------>| | | P0_P48_4 ------>| GPIO |---------------->| | | |________| | | |GPIOINT0-122 | | | | | |---------------->| TINT0-31 | | | |______| |__________| |____________| The proposed RFC patches, add the IRQ domains in GPIO (pinctrl driver) and the IRQC driver. The IRQC domain handles the actual SPI interrupt and upon reception of the interrupt it propagates to the GPIO IRQ domain to handle virq. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is handled by the IRQC driver. GPIO interrupts TINT0-T31 support rising/falling/high/low trigger, support for both falling/rising edges is handled by the SW by toggling the RISING/FALLING (we might loose interrupts, I have done limited testing for SD card detection where interrupt is requested for both rising and falling edge). Please share your valuable comments on the above implementation. Cheers, Prabhakar Lad Prabhakar (4): dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller irqchip: Add RZ/G2L IA55 Interrupt Controller driver pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt arm64: dts: renesas: r9a07g044: Add IRQC node to SoC DTSI .../renesas,rzg2l-irqc.yaml | 129 ++++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 58 ++ drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzg2l.c | 557 ++++++++++++++++++ drivers/pinctrl/renesas/pinctrl-rzg2l.c | 205 +++++++ drivers/soc/renesas/Kconfig | 1 + 7 files changed, 959 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c