From patchwork Tue Mar 23 13:09:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 406874 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4438981jai; Tue, 23 Mar 2021 06:10:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz04qGtE5mcHCjszofnK9Xc0ywmRWbNkEF8FQWlHAPn9SeHxdRL3WyR0Z4arxVNQQeTN42h X-Received: by 2002:a05:6402:1a4f:: with SMTP id bf15mr4603783edb.304.1616505040508; Tue, 23 Mar 2021 06:10:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616505040; cv=none; d=google.com; s=arc-20160816; b=WTmDnLRbjV3gytEb02BCyXsyYloiwyMzismIM36sFqHPgMz/P6EYbO9+fHALnpNO9r MeehQSld6twbORfF10ddZ4H77WdFQ9VkAtz6i7gR+jBBLcOf7nApG7OhI9bco3Yu/I6v tS8/Uh9MXC3sEBdbwW1Usq/3XdcDr44DwkovHCLZ9IaCARhx4/49SyTAGsy39FLwgy4M fv5kvZxnug7B4KMJx7vpFJ44egdUyW7x7cMtOHdSbCJ/J7HGD9yRZ/QP1FiUP+Ian8Fj nyv1cpvm3/NGVk99urY90YYpSeOwskZhxoZAMt3N7CW0FJw5F8wkmQw1L1WMH8M4fJH+ RE0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=dh4dgYbNHCso/5I5dBQcW7HgQvE62Nvy3pZOi5HXgqU=; b=IO5+kQR/vnylfjrV3Hdt6hNeajgUbWAMbL0JBUYvqMjGI77rAJjr+el8EbKwtFTa5U ixliLnFAd480HHXt7/6C69P5GDEEMw77uIWoOJ/cKbbgUaYkkFmMJfW8WYWjs1r6TPkN n9FlQfE4ddDIvqXPNG5mrkC9x6UU8qWz8lLETvR/ILpAJnW6UROtCUf/OttUPgLZUUuV xOOPxFHPDyg9ewq06Hwtr8UdzfN0xYZh7U4ngsIGvkM4EXLm5855AI2TyR993A+wxpgW o2THjAUHMqQPbohmgyfVfTaV8lC66UP86KKkv5tn2lEVfmBXCq/21r30zvzAYuXgcLtk ogWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=C6veXxYD; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 39si14624816edq.111.2021.03.23.06.10.40; Tue, 23 Mar 2021 06:10:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=C6veXxYD; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231484AbhCWNKK (ORCPT + 3 others); Tue, 23 Mar 2021 09:10:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:43948 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231301AbhCWNKH (ORCPT ); Tue, 23 Mar 2021 09:10:07 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 56F1E619A9; Tue, 23 Mar 2021 13:10:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1616505007; bh=O4d9mf5szkECVTZN9/wTulI82KmEbZJBxSHDoo1NfVM=; h=From:To:Cc:Subject:Date:From; b=C6veXxYDJwBTQanhhUpTW9g9vm/HSOPq1531lBlzKzG4zxyUfeFDKdtHUU096V+NT m6yKKo9YjY0O4+WyebJT3//quh8i5siaRTJoKP9gPAjMIIW57wdZsBd7tSsuAUbcXy oAnosuyJCo9TkoRK9yF5gN7lFpv7MRah3d6OLav29uAG+ysOLKjrGxAOOP09KfRUzx 4qEigzxHv2wdUXIvCL3fiuWDlMEumxvahxXDxTxsSCZbJxABl2odpbaReWw9kjBlAJ iU1bu1ddgv4vRWAoRHdyghSIpBXO1cQcIpb8RUgigQIKII30vBOBfC2DxxKP5++SP+ TP265wlZYQyMA== From: Arnd Bergmann To: Lars Povlsen , Steen Hegelund , UNGLinuxDriver@microchip.com, Linus Walleij Cc: Arnd Bergmann , Zou Wei , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] pinctrl: microchip: fix array overflow Date: Tue, 23 Mar 2021 14:09:51 +0100 Message-Id: <20210323131002.2418896-1-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Arnd Bergmann Building with 'make W=1' shows an array overflow: drivers/pinctrl/pinctrl-microchip-sgpio.c: In function 'microchip_sgpio_irq_settype': drivers/pinctrl/pinctrl-microchip-sgpio.c:154:39: error: array subscript 10 is above array bounds of 'const u8[10]' {aka 'const unsigned char[10]'} [-Werror=array-bounds] 154 | u32 regoff = priv->properties->regoff[rno] + off; | ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~ drivers/pinctrl/pinctrl-microchip-sgpio.c:55:5: note: while referencing 'regoff' 55 | u8 regoff[MAXREG]; | ^~~~~~ It's not clear to me what was meant here, my best guess is that the offset should have been applied to the third argument instead of the second. Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)") Signed-off-by: Arnd Bergmann --- drivers/pinctrl/pinctrl-microchip-sgpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.29.2 diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index f35edb0eac40..4740613cdd03 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -572,7 +572,7 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, /* Type value spread over 2 registers sets: low, high bit */ sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, BIT(addr.port), (!!(type & 0x1)) << addr.port); - sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit, + sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit + SGPIO_MAX_BITS, BIT(addr.port), (!!(type & 0x2)) << addr.port); if (type == SGPIO_INT_TRG_LEVEL)