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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id x15-20020a19e00f000000b00498fc3d4d15sm1079375lfg.190.2022.09.22.12.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 12:57:11 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 12/12] arm64: dts: qcom: sm8250: align LPASS pin configuration with DT schema Date: Thu, 22 Sep 2022 21:56:51 +0200 Message-Id: <20220922195651.345369-13-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922195651.345369-1-krzysztof.kozlowski@linaro.org> References: <20220922195651.345369-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org DT schema expects LPASS pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 44 ++++++++++++++-------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8f402b912c62..e0416d611b66 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2388,8 +2388,8 @@ lpass_tlmm: pinctrl@33c0000{ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "core", "audio"; - wsa_swr_active: wsa-swr-active-pins { - clk { + wsa_swr_active: wsa-swr-active-state { + clk-pins { pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; @@ -2397,7 +2397,7 @@ clk { bias-disable; }; - data { + data-pins { pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; @@ -2407,8 +2407,8 @@ data { }; }; - wsa_swr_sleep: wsa-swr-sleep-pins { - clk { + wsa_swr_sleep: wsa-swr-sleep-state { + clk-pins { pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; @@ -2416,7 +2416,7 @@ clk { bias-pull-down; }; - data { + data-pins { pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; @@ -2426,14 +2426,14 @@ data { }; }; - dmic01_active: dmic01-active-pins { - clk { + dmic01_active: dmic01-active-state { + clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <8>; output-high; }; - data { + data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; @@ -2441,8 +2441,8 @@ data { }; }; - dmic01_sleep: dmic01-sleep-pins { - clk { + dmic01_sleep: dmic01-sleep-state { + clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <2>; @@ -2450,7 +2450,7 @@ clk { output-low; }; - data { + data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <2>; @@ -2459,8 +2459,8 @@ data { }; }; - rx_swr_active: rx_swr-active-pins { - clk { + rx_swr_active: rx-swr-active-state { + clk-pins { pins = "gpio3"; function = "swr_rx_clk"; drive-strength = <2>; @@ -2468,7 +2468,7 @@ clk { bias-disable; }; - data { + data-pins { pins = "gpio4", "gpio5"; function = "swr_rx_data"; drive-strength = <2>; @@ -2477,8 +2477,8 @@ data { }; }; - tx_swr_active: tx_swr-active-pins { - clk { + tx_swr_active: tx-swr-active-state { + clk-pins { pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; @@ -2486,7 +2486,7 @@ clk { bias-disable; }; - data { + data-pins { pins = "gpio1", "gpio2"; function = "swr_tx_data"; drive-strength = <2>; @@ -2495,8 +2495,8 @@ data { }; }; - tx_swr_sleep: tx_swr-sleep-pins { - clk { + tx_swr_sleep: tx-swr-sleep-state { + clk-pins { pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; @@ -2504,7 +2504,7 @@ clk { bias-pull-down; }; - data1 { + data1-pins { pins = "gpio1"; function = "swr_tx_data"; drive-strength = <2>; @@ -2512,7 +2512,7 @@ data1 { bias-bus-hold; }; - data2 { + data2-pins { pins = "gpio2"; function = "swr_tx_data"; drive-strength = <2>;