diff mbox series

[4/8] clk: Add Ingenic JZ4755 CGU driver

Message ID 20221009181338.2896660-5-lis8215@gmail.com
State Accepted
Commit ff0d3ae04f7307ff2447ad79f38806f240fe783d
Headers show
Series MIPS: ingenic: Add support for the JZ4755 SoC | expand

Commit Message

Siarhei Volkau Oct. 9, 2022, 6:13 p.m. UTC 
Add support for the clocks provided by the CGU in the Ingenic JZ4755
SoC.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
 drivers/clk/ingenic/Kconfig      |  10 +
 drivers/clk/ingenic/Makefile     |   1 +
 drivers/clk/ingenic/jz4755-cgu.c | 350 +++++++++++++++++++++++++++++++
 3 files changed, 361 insertions(+)
 create mode 100644 drivers/clk/ingenic/jz4755-cgu.c

Comments

kernel test robot Oct. 10, 2022, 7:24 p.m. UTC | #1 
Hi Siarhei,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next vkoul-dmaengine/next linus/master v6.0 next-20221010]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: mips-randconfig-s042-20221010
compiler: mips64el-linux-gcc (GCC) 12.1.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.4-39-gce1a6720-dirty
        # https://github.com/intel-lab-lkp/linux/commit/6d24b5a35a40bad51094228d64da242aa0516d83
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Siarhei-Volkau/dt-bindings-ingenic-Add-support-for-the-JZ4755-SoC/20221010-031428
        git checkout 6d24b5a35a40bad51094228d64da242aa0516d83
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=mips SHELL=/bin/bash drivers/clk/ingenic/ drivers/tty/serial/8250/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

sparse warnings: (new ones prefixed by >>)
>> drivers/clk/ingenic/jz4755-cgu.c:94:25: sparse: sparse: Using plain integer as NULL pointer

vim +94 drivers/clk/ingenic/jz4755-cgu.c

    49	
    50		/* External clocks */
    51	
    52		[JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT },
    53		[JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
    54	
    55		[JZ4755_CLK_PLL] = {
    56			"pll", CGU_CLK_PLL,
    57			.parents = { JZ4755_CLK_EXT, -1, -1, -1 },
    58			.pll = {
    59				.reg = CGU_REG_CPPCR,
    60				.rate_multiplier = 1,
    61				.m_shift = 23,
    62				.m_bits = 9,
    63				.m_offset = 2,
    64				.n_shift = 18,
    65				.n_bits = 5,
    66				.n_offset = 2,
    67				.od_shift = 16,
    68				.od_bits = 2,
    69				.od_max = 4,
    70				.od_encoding = pll_od_encoding,
    71				.stable_bit = 10,
    72				.bypass_reg = CGU_REG_CPPCR,
    73				.bypass_bit = 9,
    74				.enable_bit = 8,
    75			},
    76		},
    77	
    78		/* Muxes & dividers */
    79	
    80		[JZ4755_CLK_PLL_HALF] = {
    81			"pll half", CGU_CLK_DIV,
    82			.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
    83			.div = {
    84				CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
    85				jz4755_cgu_pll_half_div_table,
    86			},
    87		},
    88	
    89		[JZ4755_CLK_EXT_HALF] = {
    90			"ext half", CGU_CLK_DIV,
    91			.parents = { JZ4755_CLK_EXT, -1, -1, -1 },
    92			.div = {
    93				CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
  > 94				0,
    95			},
    96		},
    97	
    98		[JZ4755_CLK_CCLK] = {
    99			"cclk", CGU_CLK_DIV,
   100			.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
   101			.div = {
   102				CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
   103				jz4755_cgu_cpccr_div_table,
   104			},
   105		},
   106	
   107		[JZ4755_CLK_H0CLK] = {
   108			"hclk", CGU_CLK_DIV,
   109			.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
   110			.div = {
   111				CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
   112				jz4755_cgu_cpccr_div_table,
   113			},
   114		},
   115	
   116		[JZ4755_CLK_PCLK] = {
   117			"pclk", CGU_CLK_DIV,
   118			.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
   119			.div = {
   120				CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
   121				jz4755_cgu_cpccr_div_table,
   122			},
   123		},
   124	
   125		[JZ4755_CLK_MCLK] = {
   126			"mclk", CGU_CLK_DIV,
   127			.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
   128			.div = {
   129				CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
   130				jz4755_cgu_cpccr_div_table,
   131			},
   132		},
   133	
   134		[JZ4755_CLK_H1CLK] = {
   135			"h1clk", CGU_CLK_DIV,
   136			.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
   137			.div = {
   138				CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
   139				jz4755_cgu_cpccr_div_table,
   140			},
   141		},
   142	
   143		[JZ4755_CLK_UDC] = {
   144			"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
   145			.parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
   146			.mux = { CGU_REG_CPCCR, 29, 1 },
   147			.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
   148			.gate = { CGU_REG_CLKGR, 10 },
   149		},
   150	
   151		[JZ4755_CLK_LCD] = {
   152			"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
   153			.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
   154			.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
   155			.gate = { CGU_REG_CLKGR, 9 },
   156		},
   157	
   158		[JZ4755_CLK_MMC] = {
   159			"mmc", CGU_CLK_DIV,
   160			.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
   161			.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
   162		},
   163	
   164		[JZ4755_CLK_I2S] = {
   165			"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
   166			.parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
   167			.mux = { CGU_REG_CPCCR, 31, 1 },
   168			.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
   169		},
   170	
   171		[JZ4755_CLK_SPI] = {
   172			"spi", CGU_CLK_DIV | CGU_CLK_GATE,
   173			.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
   174			.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
   175			.gate = { CGU_REG_CLKGR, 4 },
   176		},
   177	
   178		[JZ4755_CLK_TVE] = {
   179			"tve", CGU_CLK_MUX | CGU_CLK_GATE,
   180			.parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 },
   181			.mux = { CGU_REG_LPCDR, 31, 1 },
   182			.gate = { CGU_REG_CLKGR, 18 },
   183		},
   184	
   185		[JZ4755_CLK_RTC] = {
   186			"rtc", CGU_CLK_MUX | CGU_CLK_GATE,
   187			.parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 },
   188			.mux = { CGU_REG_OPCR, 2, 1},
   189			.gate = { CGU_REG_CLKGR, 2 },
   190		},
   191	
   192		[JZ4755_CLK_CIM] = {
   193			"cim", CGU_CLK_DIV | CGU_CLK_GATE,
   194			.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
   195			.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
   196			.gate = { CGU_REG_CLKGR, 8 },
   197		},
   198	
   199		/* Gate-only clocks */
   200	
   201		[JZ4755_CLK_UART0] = {
   202			"uart0", CGU_CLK_GATE,
   203			.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
   204			.gate = { CGU_REG_CLKGR, 0 },
   205		},
   206	
   207		[JZ4755_CLK_UART1] = {
   208			"uart1", CGU_CLK_GATE,
   209			.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
   210			.gate = { CGU_REG_CLKGR, 14 },
   211		},
   212	
   213		[JZ4755_CLK_UART2] = {
   214			"uart2", CGU_CLK_GATE,
   215			.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
   216			.gate = { CGU_REG_CLKGR, 15 },
   217		},
   218	
   219		[JZ4755_CLK_ADC] = {
   220			"adc", CGU_CLK_GATE,
   221			.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
   222			.gate = { CGU_REG_CLKGR, 7 },
   223		},
   224	
   225		[JZ4755_CLK_AIC] = {
   226			"aic", CGU_CLK_GATE,
   227			.parents = { JZ4755_CLK_I2S, -1, -1, -1 },
   228			.gate = { CGU_REG_CLKGR, 5 },
   229		},
   230	
   231		[JZ4755_CLK_I2C] = {
   232			"i2c", CGU_CLK_GATE,
   233			.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
   234			.gate = { CGU_REG_CLKGR, 3 },
   235		},
   236	
   237		[JZ4755_CLK_BCH] = {
   238			"bch", CGU_CLK_GATE,
   239			.parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 },
   240			.gate = { CGU_REG_CLKGR, 11 },
   241		},
   242	
   243		[JZ4755_CLK_TCU] = {
   244			"tcu", CGU_CLK_GATE,
   245			.parents = { JZ4755_CLK_EXT, -1, -1, -1 },
   246			.gate = { CGU_REG_CLKGR, 1 },
   247		},
   248	
   249		[JZ4755_CLK_DMA] = {
   250			"dma", CGU_CLK_GATE,
   251			.parents = { JZ4755_CLK_PCLK, -1, -1, -1 },
   252			.gate = { CGU_REG_CLKGR, 12 },
   253		},
   254	
   255		[JZ4755_CLK_MMC0] = {
   256			"mmc0", CGU_CLK_GATE,
   257			.parents = { JZ4755_CLK_MMC, -1, -1, -1 },
   258			.gate = { CGU_REG_CLKGR, 6 },
   259		},
   260	
   261		[JZ4755_CLK_MMC1] = {
   262			"mmc1", CGU_CLK_GATE,
   263			.parents = { JZ4755_CLK_MMC, -1, -1, -1 },
   264			.gate = { CGU_REG_CLKGR, 16 },
   265		},
   266	
   267		[JZ4755_CLK_AUX_CPU] = {
   268			"aux_cpu", CGU_CLK_GATE,
   269			.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
   270			.gate = { CGU_REG_CLKGR, 24 },
   271		},
   272	
   273		[JZ4755_CLK_AHB1] = {
   274			"ahb1", CGU_CLK_GATE,
   275			.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
   276			.gate = { CGU_REG_CLKGR, 23 },
   277		},
   278	
   279		[JZ4755_CLK_IDCT] = {
   280			"idct", CGU_CLK_GATE,
   281			.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
   282			.gate = { CGU_REG_CLKGR, 22 },
   283		},
   284	
   285		[JZ4755_CLK_DB] = {
   286			"db", CGU_CLK_GATE,
   287			.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
   288			.gate = { CGU_REG_CLKGR, 21 },
   289		},
   290	
   291		[JZ4755_CLK_ME] = {
   292			"me", CGU_CLK_GATE,
   293			.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
   294			.gate = { CGU_REG_CLKGR, 20 },
   295		},
   296	
   297		[JZ4755_CLK_MC] = {
   298			"mc", CGU_CLK_GATE,
   299			.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
   300			.gate = { CGU_REG_CLKGR, 19 },
   301		},
   302	
   303		[JZ4755_CLK_TSSI] = {
   304			"tssi", CGU_CLK_GATE,
   305			.parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 },
   306			.gate = { CGU_REG_CLKGR, 17 },
   307		},
   308	
   309		[JZ4755_CLK_IPU] = {
   310			"ipu", CGU_CLK_GATE,
   311			.parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 },
   312			.gate = { CGU_REG_CLKGR, 13 },
   313		},
   314	
   315		[JZ4755_CLK_EXT512] = {
   316			"ext/512", CGU_CLK_FIXDIV,
   317			.parents = { JZ4755_CLK_EXT },
   318	
   319			/* JZ4725b doc calls it EXT512, but it seems to be /256...
   320			 * Not sure if it applied to JZ4755 too, and which actual
   321			 * source is used EXT or EXT_HALF
   322			 */
   323			.fixdiv = { 256 },
   324		},
   325	
   326		[JZ4755_CLK_UDC_PHY] = {
   327			"udc_phy", CGU_CLK_GATE,
   328			.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
   329			.gate = { CGU_REG_OPCR, 6, true },
   330		},
   331	};
   332
diff mbox series

Patch

diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index 898f1bc47..f80ac4f29 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -15,6 +15,16 @@  config INGENIC_CGU_JZ4740
 
 	  If building for a JZ4740 SoC, you want to say Y here.
 
+config INGENIC_CGU_JZ4755
+	bool "Ingenic JZ4755 CGU driver"
+	default MACH_JZ4755
+	select INGENIC_CGU_COMMON
+	help
+	  Support the clocks provided by the CGU hardware on Ingenic JZ4755
+	  and compatible SoCs.
+
+	  If building for a JZ4755 SoC, you want to say Y here.
+
 config INGENIC_CGU_JZ4725B
 	bool "Ingenic JZ4725B CGU driver"
 	default MACH_JZ4725B
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 9edfaf461..81d8e23c2 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,6 +1,7 @@ 
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_INGENIC_CGU_COMMON)	+= cgu.o pm.o
 obj-$(CONFIG_INGENIC_CGU_JZ4740)	+= jz4740-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4755)	+= jz4755-cgu.o
 obj-$(CONFIG_INGENIC_CGU_JZ4725B)	+= jz4725b-cgu.o
 obj-$(CONFIG_INGENIC_CGU_JZ4760)	+= jz4760-cgu.o
 obj-$(CONFIG_INGENIC_CGU_JZ4770)	+= jz4770-cgu.o
diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c
new file mode 100644
index 000000000..98887f20b
--- /dev/null
+++ b/drivers/clk/ingenic/jz4755-cgu.c
@@ -0,0 +1,350 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Ingenic JZ4755 SoC CGU driver
+ * Heavily based on JZ4725b CGU driver
+ *
+ * Copyright (C) 2022 Siarhei Volkau
+ * Author: Siarhei Volkau <lis8215@gmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+
+#include <dt-bindings/clock/ingenic,jz4755-cgu.h>
+
+#include "cgu.h"
+#include "pm.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR		0x00
+#define CGU_REG_LCR		0x04
+#define CGU_REG_CPPCR		0x10
+#define CGU_REG_CLKGR		0x20
+#define CGU_REG_OPCR		0x24
+#define CGU_REG_I2SCDR		0x60
+#define CGU_REG_LPCDR		0x64
+#define CGU_REG_MSCCDR		0x68
+#define CGU_REG_SSICDR		0x74
+#define CGU_REG_CIMCDR		0x7C
+
+/* bits within the LCR register */
+#define LCR_SLEEP		BIT(0)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[4] = {
+	0x0, 0x1, -1, 0x3,
+};
+
+static const u8 jz4755_cgu_cpccr_div_table[] = {
+	1, 2, 3, 4, 6, 8,
+};
+
+static const u8 jz4755_cgu_pll_half_div_table[] = {
+	2, 1,
+};
+
+static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = {
+
+	/* External clocks */
+
+	[JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT },
+	[JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
+
+	[JZ4755_CLK_PLL] = {
+		"pll", CGU_CLK_PLL,
+		.parents = { JZ4755_CLK_EXT, -1, -1, -1 },
+		.pll = {
+			.reg = CGU_REG_CPPCR,
+			.rate_multiplier = 1,
+			.m_shift = 23,
+			.m_bits = 9,
+			.m_offset = 2,
+			.n_shift = 18,
+			.n_bits = 5,
+			.n_offset = 2,
+			.od_shift = 16,
+			.od_bits = 2,
+			.od_max = 4,
+			.od_encoding = pll_od_encoding,
+			.stable_bit = 10,
+			.bypass_reg = CGU_REG_CPPCR,
+			.bypass_bit = 9,
+			.enable_bit = 8,
+		},
+	},
+
+	/* Muxes & dividers */
+
+	[JZ4755_CLK_PLL_HALF] = {
+		"pll half", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
+			jz4755_cgu_pll_half_div_table,
+		},
+	},
+
+	[JZ4755_CLK_EXT_HALF] = {
+		"ext half", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_EXT, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0,
+			0,
+		},
+	},
+
+	[JZ4755_CLK_CCLK] = {
+		"cclk", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
+			jz4755_cgu_cpccr_div_table,
+		},
+	},
+
+	[JZ4755_CLK_H0CLK] = {
+		"hclk", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
+			jz4755_cgu_cpccr_div_table,
+		},
+	},
+
+	[JZ4755_CLK_PCLK] = {
+		"pclk", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
+			jz4755_cgu_cpccr_div_table,
+		},
+	},
+
+	[JZ4755_CLK_MCLK] = {
+		"mclk", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
+			jz4755_cgu_cpccr_div_table,
+		},
+	},
+
+	[JZ4755_CLK_H1CLK] = {
+		"h1clk", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL, -1, -1, -1 },
+		.div = {
+			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
+			jz4755_cgu_cpccr_div_table,
+		},
+	},
+
+	[JZ4755_CLK_UDC] = {
+		"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
+		.mux = { CGU_REG_CPCCR, 29, 1 },
+		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 10 },
+	},
+
+	[JZ4755_CLK_LCD] = {
+		"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 9 },
+	},
+
+	[JZ4755_CLK_MMC] = {
+		"mmc", CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+		.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
+	},
+
+	[JZ4755_CLK_I2S] = {
+		"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
+		.parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 },
+		.mux = { CGU_REG_CPCCR, 31, 1 },
+		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
+	},
+
+	[JZ4755_CLK_SPI] = {
+		"spi", CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+		.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 4 },
+	},
+
+	[JZ4755_CLK_TVE] = {
+		"tve", CGU_CLK_MUX | CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 },
+		.mux = { CGU_REG_LPCDR, 31, 1 },
+		.gate = { CGU_REG_CLKGR, 18 },
+	},
+
+	[JZ4755_CLK_RTC] = {
+		"rtc", CGU_CLK_MUX | CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 },
+		.mux = { CGU_REG_OPCR, 2, 1},
+		.gate = { CGU_REG_CLKGR, 2 },
+	},
+
+	[JZ4755_CLK_CIM] = {
+		"cim", CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 },
+		.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 8 },
+	},
+
+	/* Gate-only clocks */
+
+	[JZ4755_CLK_UART0] = {
+		"uart0", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 0 },
+	},
+
+	[JZ4755_CLK_UART1] = {
+		"uart1", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 14 },
+	},
+
+	[JZ4755_CLK_UART2] = {
+		"uart2", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 15 },
+	},
+
+	[JZ4755_CLK_ADC] = {
+		"adc", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 7 },
+	},
+
+	[JZ4755_CLK_AIC] = {
+		"aic", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_I2S, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 5 },
+	},
+
+	[JZ4755_CLK_I2C] = {
+		"i2c", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 3 },
+	},
+
+	[JZ4755_CLK_BCH] = {
+		"bch", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 11 },
+	},
+
+	[JZ4755_CLK_TCU] = {
+		"tcu", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 1 },
+	},
+
+	[JZ4755_CLK_DMA] = {
+		"dma", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_PCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 12 },
+	},
+
+	[JZ4755_CLK_MMC0] = {
+		"mmc0", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_MMC, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 6 },
+	},
+
+	[JZ4755_CLK_MMC1] = {
+		"mmc1", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_MMC, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 16 },
+	},
+
+	[JZ4755_CLK_AUX_CPU] = {
+		"aux_cpu", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 24 },
+	},
+
+	[JZ4755_CLK_AHB1] = {
+		"ahb1", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 23 },
+	},
+
+	[JZ4755_CLK_IDCT] = {
+		"idct", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 22 },
+	},
+
+	[JZ4755_CLK_DB] = {
+		"db", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 21 },
+	},
+
+	[JZ4755_CLK_ME] = {
+		"me", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 20 },
+	},
+
+	[JZ4755_CLK_MC] = {
+		"mc", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_H1CLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 19 },
+	},
+
+	[JZ4755_CLK_TSSI] = {
+		"tssi", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 17 },
+	},
+
+	[JZ4755_CLK_IPU] = {
+		"ipu", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 13 },
+	},
+
+	[JZ4755_CLK_EXT512] = {
+		"ext/512", CGU_CLK_FIXDIV,
+		.parents = { JZ4755_CLK_EXT },
+
+		/* JZ4725b doc calls it EXT512, but it seems to be /256...
+		 * Not sure if it applied to JZ4755 too, and which actual
+		 * source is used EXT or EXT_HALF
+		 */
+		.fixdiv = { 256 },
+	},
+
+	[JZ4755_CLK_UDC_PHY] = {
+		"udc_phy", CGU_CLK_GATE,
+		.parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 },
+		.gate = { CGU_REG_OPCR, 6, true },
+	},
+};
+
+static void __init jz4755_cgu_init(struct device_node *np)
+{
+	int retval;
+
+	cgu = ingenic_cgu_new(jz4755_cgu_clocks,
+			      ARRAY_SIZE(jz4755_cgu_clocks), np);
+	if (!cgu) {
+		pr_err("%s: failed to initialise CGU\n", __func__);
+		return;
+	}
+
+	retval = ingenic_cgu_register_clocks(cgu);
+	if (retval)
+		pr_err("%s: failed to register CGU Clocks\n", __func__);
+
+	ingenic_cgu_register_syscore_ops(cgu);
+}
+CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);