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Tue, 14 Mar 2023 13:47:04 +0000 Received: from AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9]) by AM0PR0402MB3428.eurprd04.prod.outlook.com ([fe80::2b1f:7e5:94d0:3ba9%3]) with mapi id 15.20.6178.026; Tue, 14 Mar 2023 13:47:04 +0000 From: Chester Lin To: Linus Walleij , Andy Shevchenko Cc: Chester Lin , NXP S32 Linux Team , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ghennadi Procopciuc , Andrei Stefanescu , Radu Pirea , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 2/3] pinctrl: s32cc: refactor pin config parsing Date: Tue, 14 Mar 2023 21:46:41 +0800 Message-Id: <20230314134642.21535-3-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230314134642.21535-1-clin@suse.com> References: <20230314134642.21535-1-clin@suse.com> X-ClientProxiedBy: FR0P281CA0120.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a8::10) To AM0PR0402MB3428.eurprd04.prod.outlook.com (2603:10a6:208:1a::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR0402MB3428:EE_|AS5PR04MB9895:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fa5ca3a-a43a-4796-c3da-08db2492987c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Chester Lin --- drivers/pinctrl/nxp/pinctrl-s32cc.c | 82 ++++++++++++++++++----------- 1 file changed, 50 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index 7a38e3216b0c..9508fc1e9a90 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -39,6 +39,9 @@ #define S32_MSCR_ODE BIT(20) #define S32_MSCR_OBE BIT(21) +#define S32_CFG_SET true +#define S32_CFG_CLR false + static struct regmap_config s32_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -475,32 +478,57 @@ static int s32_get_slew_regval(int arg) return -EINVAL; } -static int s32_get_pin_conf(enum pin_config_param param, u32 arg, - unsigned int *mask, unsigned int *config) +static inline void s32_pin_config(unsigned int *mask, unsigned int *config, + unsigned int bits, bool set) +{ + if (set) + *config |= bits; + else + *config &= ~bits; + *mask |= bits; +} + +static inline void s32_pull_enable(enum pin_config_param param, + unsigned int *mask, unsigned int *config) +{ + + if (param == PIN_CONFIG_BIAS_PULL_UP) { + s32_pin_config(mask, config, S32_MSCR_PUS | S32_MSCR_PUE, + S32_CFG_SET); + } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { + *config &= ~S32_MSCR_PUS; + *config |= S32_MSCR_PUE; + *mask |= S32_MSCR_PUS | S32_MSCR_PUE; + } +} + +static inline void s32_pull_disable(unsigned int *mask, unsigned int *config) +{ + s32_pin_config(mask, config, S32_MSCR_PUS | S32_MSCR_PUE, S32_CFG_CLR); +} + +static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask, + unsigned int *config) { + enum pin_config_param param; + u32 arg; int ret; + param = pinconf_to_config_param(pincfg); + arg = pinconf_to_config_argument(pincfg); + switch (param) { /* All pins are persistent over suspend */ case PIN_CONFIG_PERSIST_STATE: return 0; case PIN_CONFIG_DRIVE_OPEN_DRAIN: - *config |= S32_MSCR_ODE; - *mask |= S32_MSCR_ODE; + s32_pin_config(mask, config, S32_MSCR_ODE, S32_CFG_SET); break; case PIN_CONFIG_OUTPUT_ENABLE: - if (arg) - *config |= S32_MSCR_OBE; - else - *config &= ~S32_MSCR_OBE; - *mask |= S32_MSCR_OBE; + s32_pin_config(mask, config, S32_MSCR_OBE, S32_CFG_SET); break; case PIN_CONFIG_INPUT_ENABLE: - if (arg) - *config |= S32_MSCR_IBE; - else - *config &= ~S32_MSCR_IBE; - *mask |= S32_MSCR_IBE; + s32_pin_config(mask, config, S32_MSCR_IBE, S32_CFG_SET); break; case PIN_CONFIG_SLEW_RATE: ret = s32_get_slew_regval(arg); @@ -510,25 +538,17 @@ static int s32_get_pin_conf(enum pin_config_param param, u32 arg, *mask |= S32_MSCR_SRE(~0); break; case PIN_CONFIG_BIAS_PULL_UP: - if (arg) - *config |= S32_MSCR_PUS; - else - *config &= ~S32_MSCR_PUS; - fallthrough; case PIN_CONFIG_BIAS_PULL_DOWN: - if (arg) - *config |= S32_MSCR_PUE; - else - *config &= ~S32_MSCR_PUE; - *mask |= S32_MSCR_PUE | S32_MSCR_PUS; + s32_pull_enable(param, mask, config); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE); - *mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE; - fallthrough; + s32_pin_config(mask, config, + S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE, + S32_CFG_CLR); + s32_pull_disable(mask, config); + break; case PIN_CONFIG_BIAS_DISABLE: - *config &= ~(S32_MSCR_PUS | S32_MSCR_PUE); - *mask |= S32_MSCR_PUS | S32_MSCR_PUE; + s32_pull_disable(mask, config); break; default: return -EOPNOTSUPP; @@ -554,9 +574,7 @@ static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev, pin_get_name(pctldev, pin_id), num_configs); for (i = 0; i < num_configs; i++) { - ret = s32_get_pin_conf(pinconf_to_config_param(configs[i]), - pinconf_to_config_argument(configs[i]), - &mask, &config); + ret = s32_parse_pincfg(configs[i], &mask, &config); if (ret) return ret; }