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Thu, 13 Jan 2022 13:31:17 +0000 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH 4/6] arm64: tegra: Add Tegra234 I2C devicetree nodes Date: Thu, 13 Jan 2022 19:00:21 +0530 Message-ID: <1642080623-15980-5-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642080623-15980-1-git-send-email-akhilrajeev@nvidia.com> References: <1642080623-15980-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 60c67bfa-9a0a-483f-2e91-08d9d698fd55 X-MS-TrafficTypeDiagnostic: DM5PR12MB1563:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yDZUHlXY7M1x2IWsTWmNa+hxt4Ml68YO845gaFkl+RejtAWkEKFx+NKUvVSHC/KtVsFDrs6EFmrb5Vy4kL7MUJeFJMtlXu7dew+o0ezbCrfJlDTZ0jpBgSkZbtbXNWYseKZHHRV5V/ohlYeS5lv8DS3JF7TFfqz58dFgA0wbJL4wY5f+683cp7Jq22NKBX0Fpw/hsjQrNC3SvxUneXnrvpf6iTyQ77sqRnOge+6mVy6B/eQiqV6++TYFT7vlS//mlFaHNenKk+eEhAwzxLmYABBc3IKGuGHpmHCUB2rYlCxhoBpOcnEfwU9rHbqc9MrtnbTuoRxRu8wryOXdMXYgvJZALhYfVdavPjn2qTNuKVCxVejiMxzwjpGQLGrura2J3kbqkhrd3ox/kdQyszRtGjtvO24tys0RFPF77rpKQ2yrARWq/ohtA7D6f5w3sT9Rfns9eOaq+aOTp2fqk/c4/f80Fm48zdxjERJwnYoeWTiwLMSL2jpNxAEtOiicUjSRZHSrO7WBzQ+lVG95+RUAacDOOFtnwmYh/XAxnVm/PqvUJ4OtNsNioAv82E/he559eC/9GU1WGtCyn8fO05Ac4AyvNSnZ9npzUHW1DWvD0iS2WqwWNNkCQqrqfYGZAHJY2j8JaaVe6ZdAlxkRLQR+ZtjA5lzeXKa8fRgC28o6J16mdFDqnuIC0nPwtIUMoFJjovydIj3XotZbweDV3Q6Ei3bAZ66G6HidYFkS7fmOuEhpjDThuPu34UJqgzSNM2/sUDyZSnf9l5CmOioZl9zD+lAhPNiXgDGtyUmWFnRq59B1gPsm8jOSR4kDZSR1fHPD X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(40470700002)(46966006)(81166007)(921005)(6666004)(508600001)(36756003)(82310400004)(83380400001)(5660300002)(110136005)(7696005)(356005)(316002)(40460700001)(8936002)(186003)(86362001)(107886003)(4326008)(2616005)(70586007)(8676002)(426003)(70206006)(2906002)(26005)(47076005)(36860700001)(336012)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2022 13:31:22.1664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60c67bfa-9a0a-483f-2e91-08d9d698fd55 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1563 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add device tree nodes for Tegra234 I2C controllers Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f1580..51aff7d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -144,6 +144,96 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -212,6 +302,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra234-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>;