From patchwork Sun Oct 11 18:22:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rayagonda Kokatanur X-Patchwork-Id: 285710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_HEADER_CTYPE_ONLY, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, T_TVD_MIME_NO_HEADERS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D09C43457 for ; Sun, 11 Oct 2020 18:24:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC2D72222C for ; Sun, 11 Oct 2020 18:24:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="LriUnQOL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728741AbgJKSYL (ORCPT ); Sun, 11 Oct 2020 14:24:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728654AbgJKSYK (ORCPT ); Sun, 11 Oct 2020 14:24:10 -0400 Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49801C0613CE for ; Sun, 11 Oct 2020 11:24:10 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id e7so2324248pfn.12 for ; Sun, 11 Oct 2020 11:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RhRTVGLwMlh2VV6dvWs6BmoKc1nFs8ftRSOLRr9Wvtw=; b=LriUnQOLsxVK6KHg6Hj/y1wyCwU6XUOuo05JfquCoAE/zIDtOKxMH8N+U8tU8wUl3d U46Vxs9YfLgmLe0VZDTQsr8qPohrtLIHI4TTzyJy+wBLVuCICLsMk6mVWRRXfz2NTE/Z AsnGSIqeLjEEw74f9dxL52IqQUFgptLUHdnh0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RhRTVGLwMlh2VV6dvWs6BmoKc1nFs8ftRSOLRr9Wvtw=; b=A6eHUUgc19VUsafi5q8nPJyupuNND2ieoonOP47Uh+vnDAAoy7i3so9wIXC7uSdYoj W44lOIIAtWqUHf3tuv+pqk4YdkY0IDHROS2LOXmAirkYiD6lNkrSDOA83wzI4He67J+r vL9nOUxSLk5yWLq5rHO62wbAc6t+pn4An2xehQpnEU5YmmaGGJehEZ90Cg3qfC/4p0bO jY2z7nibn2ogiq8EbDRGwT9b+onAyUvoDeAECYJ8rRsx/w9zxrZ48CSwv2JtiSul/yGg XUz4bnzsYBo7bIm4LUWm0qX4B4U/RUgIXjKAotKJvfo9u8b1Tg69+ONcl+OsgrdCLQ8Y g6YA== X-Gm-Message-State: AOAM5311AZlLR0iQg71ZIdgLKFLTQ0dFp7lGo73i/T4pMYcOIAsd/t0p vxw1TLQLtUwGfE0Xq8Izaq1Oiw== X-Google-Smtp-Source: ABdhPJxjqJEt4ZIII9dcTR8qfMSvBlv8jI3OBCkW4g45W0sHiVbrznvCOoz2STsZgpv2Xswh4QPaGw== X-Received: by 2002:a17:90a:d80e:: with SMTP id a14mr15875676pjv.168.1602440649673; Sun, 11 Oct 2020 11:24:09 -0700 (PDT) Received: from rayagonda.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id g1sm21977807pjj.3.2020.10.11.11.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2020 11:24:09 -0700 (PDT) From: Rayagonda Kokatanur To: Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Wolfram Sang , Florian Fainelli , Brendan Higgins , Andy Shevchenko , Lori Hikichi , Dhananjay Phadke , linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rayagonda Kokatanur Subject: [PATCH v1 6/6] i2c: iproc: handle rx fifo full interrupt Date: Sun, 11 Oct 2020 23:52:54 +0530 Message-Id: <20201011182254.17776-7-rayagonda.kokatanur@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201011182254.17776-1-rayagonda.kokatanur@broadcom.com> References: <20201011182254.17776-1-rayagonda.kokatanur@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add code to handle IS_S_RX_FIFO_FULL_SHIFT interrupt to support master write request with >= 64 bytes. Iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes full. This can happen if master issues write request of more than 64 bytes. Signed-off-by: Rayagonda Kokatanur --- drivers/i2c/busses/i2c-bcm-iproc.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index 22e04055b447..cceaf69279a9 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -313,6 +313,8 @@ static void bcm_iproc_i2c_slave_init( /* Enable interrupt register to indicate a valid byte in receive fifo */ val = BIT(IE_S_RX_EVENT_SHIFT); + /* Enable interrupt register to indicate Slave Rx FIFO Full */ + val |= BIT(IE_S_RX_FIFO_FULL_SHIFT); /* Enable interrupt register to indicate a Master read transaction */ val |= BIT(IE_S_RD_EVENT_SHIFT); /* Enable interrupt register for the Slave BUSY command */ @@ -434,9 +436,15 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, * events * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT * events or only IS_S_RD_EVENT_SHIFT + * + * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt + * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes + * full. This can happen if Master issues write requests of more than + * 64 bytes. */ if (status & BIT(IS_S_RX_EVENT_SHIFT) || - status & BIT(IS_S_RD_EVENT_SHIFT)) { + status & BIT(IS_S_RD_EVENT_SHIFT) || + status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) { /* disable slave interrupts */ val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val &= ~iproc_i2c->slave_int_mask; @@ -452,9 +460,14 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, /* schedule tasklet to read data later */ tasklet_schedule(&iproc_i2c->slave_rx_tasklet); - /* clear only IS_S_RX_EVENT_SHIFT interrupt */ - iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, - BIT(IS_S_RX_EVENT_SHIFT)); + /* + * clear only IS_S_RX_EVENT_SHIFT and + * IS_S_RX_FIFO_FULL_SHIFT interrupt. + */ + val = BIT(IS_S_RX_EVENT_SHIFT); + if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) + val |= BIT(IS_S_RX_FIFO_FULL_SHIFT); + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val); } if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {