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[v5,06/10] i2c: npcm: Correct register access width

Message ID 20220517101142.28421-7-warp5tw@gmail.com
State New
Headers show
Series i2c: npcm: Bug fixes timeout, spurious interrupts | expand

Commit Message

Tyrone Ting May 17, 2022, 10:11 a.m. UTC 
From: Tyrone Ting <kfting@nuvoton.com>

The SMBnCTL3 register is 8-bit wide and the 32-bit access was always
incorrect, but simply didn't cause a visible error on the 32-bit machine.

On the 64-bit machine, the kernel message reports that ESR value is
0x96000021. Checking Arm Architecture Reference Manual Armv8 suggests that
it's the alignment fault.

SMBnCTL3's address is 0xE.

Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
---
 drivers/i2c/busses/i2c-npcm7xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Wolfram Sang May 21, 2022, 5:53 a.m. UTC | #1 
On Tue, May 17, 2022 at 06:11:38PM +0800, Tyrone Ting wrote:
> From: Tyrone Ting <kfting@nuvoton.com>
> 
> The SMBnCTL3 register is 8-bit wide and the 32-bit access was always
> incorrect, but simply didn't cause a visible error on the 32-bit machine.
> 
> On the 64-bit machine, the kernel message reports that ESR value is
> 0x96000021. Checking Arm Architecture Reference Manual Armv8 suggests that
> it's the alignment fault.
> 
> SMBnCTL3's address is 0xE.
> 
> Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
> Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

Applied to for-next, thanks!
Tyrone Ting May 21, 2022, 12:58 p.m. UTC | #2 
Hi Wolfram:

Thank you for your help.

Wolfram Sang <wsa@kernel.org> 於 2022年5月21日 週六 下午1:53寫道：
>
> On Tue, May 17, 2022 at 06:11:38PM +0800, Tyrone Ting wrote:
> > From: Tyrone Ting <kfting@nuvoton.com>
> >
> > The SMBnCTL3 register is 8-bit wide and the 32-bit access was always
> > incorrect, but simply didn't cause a visible error on the 32-bit machine.
> >
> > On the 64-bit machine, the kernel message reports that ESR value is
> > 0x96000021. Checking Arm Architecture Reference Manual Armv8 suggests that
> > it's the alignment fault.
> >
> > SMBnCTL3's address is 0xE.
> >
> > Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
> > Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
> > Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
>
> Applied to for-next, thanks!
>

Best Regards,
Tyrone
diff mbox series

Patch

diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c
index 36f8aa7ab106..58d7175f0362 100644
--- a/drivers/i2c/busses/i2c-npcm7xx.c
+++ b/drivers/i2c/busses/i2c-npcm7xx.c
@@ -360,14 +360,14 @@  static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
 {
 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 
-	return !!(I2CCTL3_SCL_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
+	return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 }
 
 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
 {
 	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 
-	return !!(I2CCTL3_SDA_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
+	return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 }
 
 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)