| Message ID | 20240510-zve-detection-v5-0-0711bdd26c12@sifive.com |
|---|---|
| Headers | show |
| Series | Support Zve32[xf] and Zve64[xfd] Vector subextensions | expand |
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Fri, 10 May 2024 00:26:50 +0800 you wrote: > The series composes of two parts. The first part Specifically, > patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how > vlenb is observed by the system. Patch 2 fixes the issue by failing the > boot process of a secondary core if vlenb mismatches. > > Here is the organization of the series: > - Patch 1, 2 provide a fix for mismatching vlen problem [1]. The > solution is to fail secondary cores if their vlenb is not the same as > the boot core. > - Patch 3 is a cleanup for introducing ZVE* Vector subextensions. It > gives the obsolete ISA parser the ability to expand ISA extensions for > sigle letter extensions. > - Patch 4, 5, 6 introduce Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa > parsing and hwprobe, and document about it. > - Patch 7 makes has_vector() check against ZVE32X instead of V, so most > userspace Vector supports will be available for bare ZVE32X. > - Patch 8 updates the prctl test so that it runs on ZVE32X. > > [...] Here is the summary with links: - [v5,1/8] riscv: vector: add a comment when calling riscv_setup_vsize() https://git.kernel.org/riscv/c/77afe3e514b8 - [v5,2/8] riscv: smp: fail booting up smp if inconsistent vlen is detected https://git.kernel.org/riscv/c/38a94c46660f - [v5,3/8] riscv: cpufeature: call match_isa_ext() for single-letter extensions https://git.kernel.org/riscv/c/98a5700dfaec - [v5,4/8] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description https://git.kernel.org/riscv/c/037df2966afc - [v5,5/8] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection https://git.kernel.org/riscv/c/1e7483542bf8 - [v5,6/8] riscv: hwprobe: add zve Vector subextensions into hwprobe interface https://git.kernel.org/riscv/c/de8f8282a969 - [v5,7/8] riscv: vector: adjust minimum Vector requirement to ZVE32X https://git.kernel.org/riscv/c/ac295b67422d - [v5,8/8] selftest: run vector prctl test for ZVE32X https://git.kernel.org/riscv/c/edc96a2b4c79 You are awesome, thank you!
The series composes of two parts. The first part Specifically, patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how vlenb is observed by the system. Patch 2 fixes the issue by failing the boot process of a secondary core if vlenb mismatches. Here is the organization of the series: - Patch 1, 2 provide a fix for mismatching vlen problem [1]. The solution is to fail secondary cores if their vlenb is not the same as the boot core. - Patch 3 is a cleanup for introducing ZVE* Vector subextensions. It gives the obsolete ISA parser the ability to expand ISA extensions for sigle letter extensions. - Patch 4, 5, 6 introduce Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe, and document about it. - Patch 7 makes has_vector() check against ZVE32X instead of V, so most userspace Vector supports will be available for bare ZVE32X. - Patch 8 updates the prctl test so that it runs on ZVE32X. The series is tested on a QEMU and verified that booting, Vector programs context-switch, signal, ptrace, prctl interfaces works when we only report partial V from the ISA. Note that the signal test was performed after applying the commit c27fa53b858b ("riscv: Fix vector state restore in rt_sigreturn()") This patch should be able to apply on risc-v for-next branch on top of the commit 0a16a1728790 ("riscv: select ARCH_HAS_FAST_MULTIPLIER") [1]: https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u Changes in v5: - Rebase on top of for-next - Update comments (1, 7) - Reorder the documentation patch to the front of patches that it documents about. (5->4) - Include ZVE64D to the list, which single letter V implies (6) - Remove ZVE32F_IMPLY_LIST (5) - Change the semantic of has_vector() thus rewrite patch 7 - Remove the patch that fixes integer promotion as it is merged else place (8) - Link to v4: https://lore.kernel.org/r/20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com Changes in v4: - Add a patch to trigger prctl test on ZVE32X (9) - Add a patch to fix integer promotion bug in hwprobe (8) - Fix a build fail on !CONFIG_RISCV_ISA_V (7) - Add more comment in the assembly code change (2) - Link to v3: https://lore.kernel.org/r/20240318-zve-detection-v3-0-e12d42107fa8@sifive.com Changelog v3: - Include correct maintainers and mailing list into CC. - Cleanup isa string parser code (3) - Adjust extensions order and name (4, 5) - Refine commit message (6) Changelog v2: - Update comments and commit messages (1, 2, 7) - Refine isa_exts[] lists for zve extensions (4) - Add a patch for dt-binding (5) - Make ZVE* extensions depend on has_vector(ZVE32X) (6, 7) --- --- Andy Chiu (8): riscv: vector: add a comment when calling riscv_setup_vsize() riscv: smp: fail booting up smp if inconsistent vlen is detected riscv: cpufeature: call match_isa_ext() for single-letter extensions dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection riscv: hwprobe: add zve Vector subextensions into hwprobe interface riscv: vector: adjust minimum Vector requirement to ZVE32X selftest: run vector prctl test for ZVE32X Documentation/arch/riscv/hwprobe.rst | 15 ++++++ .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++ arch/riscv/include/asm/hwcap.h | 5 ++ arch/riscv/include/asm/vector.h | 10 ++-- arch/riscv/include/uapi/asm/hwprobe.h | 5 ++ arch/riscv/kernel/cpufeature.c | 60 +++++++++++++++++++--- arch/riscv/kernel/head.S | 19 ++++--- arch/riscv/kernel/smpboot.c | 14 +++-- arch/riscv/kernel/sys_hwprobe.c | 11 +++- arch/riscv/kernel/vector.c | 5 +- arch/riscv/lib/uaccess.S | 2 +- .../testing/selftests/riscv/vector/vstate_prctl.c | 6 +-- 12 files changed, 151 insertions(+), 31 deletions(-) --- base-commit: 0a16a172879012c42f55ae8c2883e17c1e4e388f change-id: 20240318-zve-detection-50106d2da527 Best regards,