@@ -170,6 +170,7 @@
cbz x1, .Lskip_fgt_\@
mov x0, xzr
+ mov x2, xzr
mrs x1, id_aa64dfr0_el1
ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
cmp x1, #3
@@ -217,10 +218,14 @@
orr x0, x0, #HFGxTR_EL2_nGCS_EL1_MASK
orr x0, x0, #HFGxTR_EL2_nGCS_EL0_MASK
+ orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK
+ orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK
+ orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK
+
.Lset_fgt_\@:
msr_s SYS_HFGRTR_EL2, x0
msr_s SYS_HFGWTR_EL2, x0
- msr_s SYS_HFGITR_EL2, xzr
+ msr_s SYS_HFGITR_EL2, x2
mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
The initial EL2 setup for GCS did not include disabling of EL1 usage of GCS instructions, also disable these traps. This is the first disabling of instruction traps, use x2 to store the value to be written. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/include/asm/el2_setup.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)