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Thu, 10 Apr 2025 23:38:29 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 14/16] iommu/arm-smmu-v3: Add vsmmu_alloc impl op Date: Thu, 10 Apr 2025 23:37:53 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F0:EE_|BN7PPF0FD1DEA27:EE_ X-MS-Office365-Filtering-Correlation-Id: 3535baf5-f58c-4c9d-bff0-08dd78c38061 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: ULv9ZKOvjh/1WhHFspUGCR0cdFyOuAf/M928Xi0+u+S/4oR8hZUyPa9fLb716XVCKnpM8LQfnT5huv7X7HrkoRDVA98Z1C5xX1QccDAhBi4LV/74Nm6uahirK8tNRRPVX76eyAvE6FrUWQ07Aa0d77Es+/yh5GiRqvWSX6rKdiv/prZRNrPS2eo4FvZg+f/IN9NL70V6bD6Img3Sdu0B1O9bpkaWgraVS/kX6HzpMQG5RlP2ULPLxGhTTRIXOmKpnHJBl3uGrqBzJexlWhVMBZB6wgZ2JwqV3Zo/FyD99CdAnb/soTfSWvcTC7tkOVynwQbTLWTNSCXg9jc3NSqVVmTvVEmzmotrhlSIIa/XQICUWV0rRIsUjYIyHAo7Lqpi/Iqim9cDf5CEagOTplXb2LPycuXOBByiydPc95eMDKLso9OC2iXaTiR+cJuRU8m/gJq65pfcRlZ3g3xPyNN0RmvyLrw2phJzUa4XAAsd2vmBSNW8Iwc1K1EbHktS0HVy4SyLLHkpYd4U2NmjzjkkL9qVXc2TQxPoEwOCMpCJNrO9eaMuNSlJgN0FhOPp0Tenagx/hdm9hMhTbRv+1dkACWASZBPLTpNgI4s7tQdrycPSuoCeC5UoeCED+nPgcZ72Skz2d3nEU5s/YwDbo9bqj34xHIjUwfzm7vGwNI6bw9qZUbr+CAhHU012UMeQtHtsK11FAZGPiJaF+otipZwwXLQYJ9t46XFN6ILay4O2N6wBh+h0EoL/h72OFRkUVcjs3HxnlgJCvh4gSqw+AUbs0XQO87BXTzW2205rfYDxUW5Ghs0PmzMWxULj96aAgN/MPFqBQG4nJRep3V8RhmOWALnGgf1UFEGYkTpzp7uiLpemwwF6ZYw4XjgXGXXBAjkYgObdncRZKyINIUXAYB/En+QKzzSH24O9LKtZ6c1H/vnnFAOXzj2pCfwwzbX4MA3efNPHn1hR9dXj04o7ZYTDFJRoGUUktWDBWS7WEhOQqTcShD4q+rn7YFkqd9TMlcmgaNAaP4pdxHew294dz3icv46YeRBD6BAxJy4AdIvQi7Dx84qw2iW/R5n9vbh6nhGN5eqqoDdde4mKXy2YfE5UCPpZMaP7Yib5iodJxxCwssxWpP0cnZ3/5n+Yv0yWFQ8hH0HcO2FPQlXhDN2m3+ERr5vrSaZl3JhSgkTim/YS8JMD/4owT62PGI3ZS4dDjiyaD9m6CGwpLLTxU8DwIMvI2JljZ2w9f4S8/dvqjWrYQ0btbQgPcbFw1oz9LPzhwCRnA1B/Z6W8xxa0CygbthLY6RrFQDzvjFE3XPOzJtESHj1BohGpCGNKhIKxi8itbN05ofcU+saexxYA7IgXOFzis+kDnV9M2IGR7w8kegQRbY++MfaYfiYjTE5MPQ1SxTtK7RZlQkCRK54gYF56kp8yGkZJ8F8SNjrUyCmx8cokJIldYhMt6vQuCNpdSiGuw95V+eKi3+lTYONS1zAF54p9ljdstW4tVsIpDLmbjvygYMKGMfp11lIozO3w1ujO8pVF X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 06:38:42.4011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3535baf5-f58c-4c9d-bff0-08dd78c38061 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF0FD1DEA27 An impl driver might support its own vIOMMU object, as the following patch will add IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV. Add a vsmmu_alloc op to give impl a try, upon failure fallback to standard vsmmu allocation for IOMMU_VIOMMU_TYPE_ARM_SMMUV3. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 17 +++++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6b8f0d20dac3..a5835af72417 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -16,6 +16,7 @@ #include struct arm_smmu_device; +struct arm_smmu_domain; /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 @@ -720,6 +721,11 @@ struct arm_smmu_impl_ops { int (*init_structures)(struct arm_smmu_device *smmu); struct arm_smmu_cmdq *(*get_secondary_cmdq)( struct arm_smmu_device *smmu, struct arm_smmu_cmdq_ent *ent); + struct arm_vsmmu *(*vsmmu_alloc)( + struct arm_smmu_device *smmu, + struct arm_smmu_domain *smmu_domain, struct iommufd_ctx *ictx, + unsigned int viommu_type, + const struct iommu_user_data *user_data); }; /* An SMMUv3 instance */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 66855cae775e..aa8653af50f2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -392,10 +392,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, iommu_get_iommu_dev(dev, struct arm_smmu_device, iommu); struct arm_smmu_master *master = dev_iommu_priv_get(dev); struct arm_smmu_domain *s2_parent = to_smmu_domain(parent); - struct arm_vsmmu *vsmmu; - - if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) - return ERR_PTR(-EOPNOTSUPP); + struct arm_vsmmu *vsmmu = NULL; if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) return ERR_PTR(-EOPNOTSUPP); @@ -423,8 +420,16 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return ERR_PTR(-EOPNOTSUPP); - vsmmu = iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, - &arm_vsmmu_ops); + if (master->smmu->impl_ops && master->smmu->impl_ops->vsmmu_alloc) + vsmmu = master->smmu->impl_ops->vsmmu_alloc( + master->smmu, s2_parent, ictx, viommu_type, user_data); + if (PTR_ERR(vsmmu) == -EOPNOTSUPP) { + if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return ERR_PTR(-EOPNOTSUPP); + /* Fallback to standard SMMUv3 type if viommu_type matches */ + vsmmu = iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, + &arm_vsmmu_ops); + } if (IS_ERR(vsmmu)) return ERR_CAST(vsmmu);