From patchwork Wed Oct 30 10:53:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 839732 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C31C11E3787; Wed, 30 Oct 2024 10:54:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285673; cv=none; b=ulqgnF/pZZJRQZu0ckLdC7Nd5ZfAp2sDoXTXiDqVYsrIWUXg2VtzHnTKpr/0OexNuorV2yDDQLgTGz/Npkeem9ktl/bCu8dHT8Bsg/Q8YfThzOUMKi4WfA49viLHKEBZPGVc7ugAHBBu622G2UzuAvOSDAFBm0IxOex4K3tRqK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730285673; c=relaxed/simple; bh=1Da0IDiPucHNSI+CXCcEtNg/UlUipsEqhvsHqz5CZgU=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=NbHiPfwYxdJIuE9rAVjvYTq7iclCitvzZvlqHgIQz5w2dKtchl4GOnztDbuAZ9ZDdcdudzd+IssRYucfROoB2H80FHmQYC3HYm8WPVNkAbCgrSp4E3qPdLEwwQeXxywIgKS+/p5SciTPRt+tumlb1DJqFDJS1HA7hdwNzIXB9OE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=LdXOC2cY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LdXOC2cY" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49UATGCj028362; Wed, 30 Oct 2024 10:54:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=4nneJZ/tkv5Wps64EEwbuc C9EgRrZX1VyDoag3u69ow=; b=LdXOC2cY5DeZ4pF7eapKIG3AT6rcs++nKdfP29 OxDz1w7t/TdHHIvos/wAedDdQSHQMEmpI0M8V7Uucnb0e6MHGFEFgDSjT+uv5pgs F4uJmn3x5IUoPwK3Suv5wp0YdwCMUl5YzZkqwPEZBrhvvvJ3hHJ6XqgDCKVntqHq h4UKYoxJ/0061dvsGX6kDQrb8p6B0dt8qC/rJVkWrqhw106JQEo7NcwLjWMCV8Hk rmT6qf/lAzeeznnA4d+/+WfxFEImqTFndesUHYBPzEW+4lwE3zuc6KGdI9mkJqrp +NDdtHfoO6nq+LD28KJX79N7VkNZH6g5Tf8KCkkyH3GYzIRQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42grt73k97-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 10:54:19 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49UAsIET015340 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 10:54:18 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 03:54:08 -0700 From: Vikram Sharma To: , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Date: Wed, 30 Oct 2024 16:23:41 +0530 Message-ID: <20241030105347.2117034-1-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fp7mfYV_mEXXm3OuCViUAq4uXaITKw0E X-Proofpoint-GUID: fp7mfYV_mEXXm3OuCViUAq4uXaITKw0E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300084 SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY, CSID, VFE/RDI interfaces in SC7280. SC7280 provides - 3 x VFE, 3 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE - 3 x CSID - 2 x CSID Lite - 5 x CSI PHY The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine the base dts for qcs6490-rb3gen2 is: https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/ Changes in V4: - V3 had 8 patches and V4 is reduced to 6. - Removed [Patch v3 2/8] as binding change is not required for dtso. - Removed [Patch v3 3/8] as the fix is already taken care in latest kernel tip. - Updated alignment for dtsi and dt-bindings. - Adding qcs6490-rb3gen2-vision-mezzanine as overlay. - Link to v3: https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/ Changes in V3: - Added missed subject line for cover letter of V2. - Updated Alignment, indentation and properties order. - edit commit text for [PATCH 02/10] and [PATCH 03/10]. - Refactor camss_link_entities. - Removed camcc enablement changes as it already done. - Link to v2: https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/ Changes in V2: - Improved indentation/formatting. - Removed _src clocks and misleading code comments. - Added name fields for power domains and csid register offset in DTSI. - Dropped minItems field from YAML file. - Listed changes in alphabetical order. - Updated description and commit text to reflect changes - Changed the compatible string from imx412 to imx577. - Added board-specific enablement changes in the newly created vision board DTSI file. - Fixed bug encountered during testing. - Moved logically independent changes to a new/seprate patch. - Removed cci0 as no sensor is on this port and MCLK2, which was a copy-paste error from the RB5 board reference. - Added power rails, referencing the RB5 board. - Discarded Patch 5/6 completely (not required). - Removed unused enums. - Link to v1: https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/ Suresh Vankadara (1): media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma (5): media: dt-bindings: media: camss: Add qcom,sc7280-camss binding media: qcom: camss: Sort CAMSS version enums and compatible strings media: qcom: camss: Restructure camss_link_entities arm64: dts: qcom: sc7280: Add support for camss arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine .../bindings/media/qcom,sc7280-camss.yaml | 439 +++++++++++++++ arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcs6490-rb3gen2-vision-mezzanine.dtso | 73 +++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 208 ++++++++ .../media/platform/qcom/camss/camss-csid.c | 1 - .../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +- .../media/platform/qcom/camss/camss-csiphy.c | 5 + .../media/platform/qcom/camss/camss-csiphy.h | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 8 +- drivers/media/platform/qcom/camss/camss.c | 500 ++++++++++++++++-- drivers/media/platform/qcom/camss/camss.h | 1 + 11 files changed, 1190 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso