From patchwork Wed Aug 31 13:25:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 75097 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp336880qga; Wed, 31 Aug 2016 06:26:00 -0700 (PDT) X-Received: by 10.66.50.9 with SMTP id y9mr17053241pan.88.1472649960035; Wed, 31 Aug 2016 06:26:00 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e11si50937565pal.229.2016.08.31.06.25.59; Wed, 31 Aug 2016 06:26:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-media-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-media-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933073AbcHaNZi (ORCPT + 4 others); Wed, 31 Aug 2016 09:25:38 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:17365 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754570AbcHaNZe (ORCPT ); Wed, 31 Aug 2016 09:25:34 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OCR002DZZYJ5C10@mailout4.w1.samsung.com>; Wed, 31 Aug 2016 14:25:31 +0100 (BST) X-AuditID: cbfec7f5-f792e6d0000013f5-eb-57c6dac9ef34 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 4A.04.05109.9CAD6C75; Wed, 31 Aug 2016 14:25:29 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OCR00GVUZYCHR60@eusync1.samsung.com>; Wed, 31 Aug 2016 14:25:29 +0100 (BST) From: Marek Szyprowski To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski Subject: [PATCH 3/3] ARM: exynos: add all required FIMC-IS clocks to exynos4x12 dtsi Date: Wed, 31 Aug 2016 15:25:18 +0200 Message-id: <1472649918-10371-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1472649918-10371-1-git-send-email-m.szyprowski@samsung.com> References: <1472649918-10371-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNJMWRmVeSWpSXmKPExsVy+t/xy7onbx0LN9jQpG3x+oWhRc+GrawW M87vY7JYe+Quu8XhN+2sDqwefVtWMXp83iQXwBTFZZOSmpNZllqkb5fAlTFx5VOWgnauigU7 vrM3MP5k72Lk5JAQMJH4/vMIlC0mceHeerYuRi4OIYGljBJfn91hh3CamCR+NP1nAqliEzCU 6HrbxQZiiwg4SSyc9ResiFmgn1Hi4/srYKOEBcIkur8+YwGxWQRUJY5+vgLWzCvgIbF5Twsb xDo5iZPHJrOC2JwCnhLTb84Bs4VAahr+sExg5F3AyLCKUTS1NLmgOCk910ivODG3uDQvXS85 P3cTIyRIvu5gXHrM6hCjAAejEg/vgVlHw4VYE8uKK3MPMUpwMCuJ8N6/cSxciDclsbIqtSg/ vqg0J7X4EKM0B4uSOO/MXe9DhATSE0tSs1NTC1KLYLJMHJxSDYxS1VsWlV3nuyr+hIl/d6PO tsobpu6L9Tm0vkmpzW48ccObUXR3ycumPTOvLDJ7t231tuV+R+YG5yZeLbxZdJFlo/bua3+W Luwtmnko8yGjvhLDmXkhIpN3PgreFCX41aEp+qYobxovr+IUFxHhpZ9SiuuyzdI/+7V3z76w Skor+dvvS29+PLyvxFKckWioxVxUnAgAZcZP6w4CAAA= Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org FIMC-IS blocks must control 3 more clocks ("gicisp", "mcuctl_isp" and "pwm_isp") to make the hardware fully operational. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos4x12.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c452499ae8c9..3394bdcf10ae 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -157,7 +157,9 @@ <&clock CLK_MOUT_MPLL_USER_T>, <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, + <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, + <&clock CLK_PWM_ISP>, + <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, <&clock CLK_DIV_MCUISP0>, <&clock CLK_DIV_MCUISP1>, <&clock CLK_UART_ISP_SCLK>, @@ -167,6 +169,7 @@ clock-names = "lite0", "lite1", "ppmuispx", "ppmuispmx", "mpll", "isp", "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "uart", "aclk200", "div_aclk200", "aclk400mcuisp",