From patchwork Fri Apr 3 09:40:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xia Jiang X-Patchwork-Id: 210322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BF7DC2BA19 for ; Fri, 3 Apr 2020 09:41:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2AB9E21655 for ; Fri, 3 Apr 2020 09:41:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="OcL2SsDy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403894AbgDCJld (ORCPT ); Fri, 3 Apr 2020 05:41:33 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:51482 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2403818AbgDCJlI (ORCPT ); Fri, 3 Apr 2020 05:41:08 -0400 X-UUID: 3c3145dbd02345a0887e58ea125de1ab-20200403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=C7gYmaCUU4cSRDwLJUXyiRJoVdUsllJH8boXNnM767E=; b=OcL2SsDylc4nM3OpzC4JH7U1bSiOnHjlxFhe1jGtgOGu0oBFZxqdTI9OMun1sax1Njz4a+TP1cFYzqjPS9cG5sTPxH5uDlHI/9nZaxf1631pncVAe3p/N+J4fgtf0bewnzbA+hqxBSwrPG0Jh8fFpISziJNIlBoXHl6wOvPy3/s=; X-UUID: 3c3145dbd02345a0887e58ea125de1ab-20200403 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 349254074; Fri, 03 Apr 2020 17:41:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 3 Apr 2020 17:40:41 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 3 Apr 2020 17:40:40 +0800 From: Xia Jiang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , "Matthias Brugger" , Rick Chang CC: , , , , , Marek Szyprowski , Tomasz Figa , , , , , , , Xia Jiang Subject: [PATCH v8 08/14] media: platform: Change case for improving code quality Date: Fri, 3 Apr 2020 17:40:27 +0800 Message-ID: <20200403094033.8288-9-xia.jiang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200403094033.8288-1-xia.jiang@mediatek.com> References: <20200403094033.8288-1-xia.jiang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Change register offset hex numberals from upercase to lowercase. Signed-off-by: Xia Jiang --- v8: no changes --- drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- 2.18.0 diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h index 94db04e9cdb6..2945da842dfa 100644 --- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h +++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h @@ -20,29 +20,29 @@ #define BIT_INQST_MASK_ALLIRQ 0x37 #define JPGDEC_REG_RESET 0x0090 -#define JPGDEC_REG_BRZ_FACTOR 0x00F8 -#define JPGDEC_REG_DU_NUM 0x00FC +#define JPGDEC_REG_BRZ_FACTOR 0x00f8 +#define JPGDEC_REG_DU_NUM 0x00fc #define JPGDEC_REG_DEST_ADDR0_Y 0x0140 #define JPGDEC_REG_DEST_ADDR0_U 0x0144 #define JPGDEC_REG_DEST_ADDR0_V 0x0148 -#define JPGDEC_REG_DEST_ADDR1_Y 0x014C +#define JPGDEC_REG_DEST_ADDR1_Y 0x014c #define JPGDEC_REG_DEST_ADDR1_U 0x0150 #define JPGDEC_REG_DEST_ADDR1_V 0x0154 #define JPGDEC_REG_STRIDE_Y 0x0158 -#define JPGDEC_REG_STRIDE_UV 0x015C +#define JPGDEC_REG_STRIDE_UV 0x015c #define JPGDEC_REG_IMG_STRIDE_Y 0x0160 #define JPGDEC_REG_IMG_STRIDE_UV 0x0164 -#define JPGDEC_REG_WDMA_CTRL 0x016C +#define JPGDEC_REG_WDMA_CTRL 0x016c #define JPGDEC_REG_PAUSE_MCU_NUM 0x0170 -#define JPGDEC_REG_OPERATION_MODE 0x017C +#define JPGDEC_REG_OPERATION_MODE 0x017c #define JPGDEC_REG_FILE_ADDR 0x0200 -#define JPGDEC_REG_COMP_ID 0x020C +#define JPGDEC_REG_COMP_ID 0x020c #define JPGDEC_REG_TOTAL_MCU_NUM 0x0210 #define JPGDEC_REG_COMP0_DATA_UNIT_NUM 0x0224 -#define JPGDEC_REG_DU_CTRL 0x023C +#define JPGDEC_REG_DU_CTRL 0x023c #define JPGDEC_REG_TRIG 0x0240 #define JPGDEC_REG_FILE_BRP 0x0248 -#define JPGDEC_REG_FILE_TOTAL_SIZE 0x024C +#define JPGDEC_REG_FILE_TOTAL_SIZE 0x024c #define JPGDEC_REG_QT_ID 0x0270 #define JPGDEC_REG_INTERRUPT_STATUS 0x0274 #define JPGDEC_REG_STATUS 0x0278