diff mbox series

[v6,02/16] dt-bindings: media: mediatek: mdp3: split out general properties

Message ID 20230922072116.11009-3-moudy.ho@mediatek.com
State New
Headers show
Series introduce more MDP3 components in MT8195 | expand

Commit Message

Moudy Ho Sept. 22, 2023, 7:21 a.m. UTC
In order to minimize duplication and standardize the document style,
it is necessary to separate the general properties specific to
MediaTek MDP3 RDMA.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
 .../media/mediatek,mdp3-rdma-common.yaml      | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-common.yaml

Comments

Krzysztof Kozlowski Sept. 23, 2023, 4:42 p.m. UTC | #1
On 22/09/2023 09:21, Moudy Ho wrote:
> In order to minimize duplication and standardize the document style,
> it is necessary to separate the general properties specific to
> MediaTek MDP3 RDMA.
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
>  .../media/mediatek,mdp3-rdma-common.yaml      | 72 +++++++++++++++++++
>  1 file changed, 72 insertions(+)

I don't understand why this is a separate patch. It's not used, not
effective and not visible for us how it extracts common parts.

Best regards,
Krzysztof
Moudy Ho Oct. 3, 2023, 3:29 a.m. UTC | #2
On Sat, 2023-09-23 at 18:42 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 22/09/2023 09:21, Moudy Ho wrote:
> > In order to minimize duplication and standardize the document
> style,
> > it is necessary to separate the general properties specific to
> > MediaTek MDP3 RDMA.
> > 
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> >  .../media/mediatek,mdp3-rdma-common.yaml      | 72
> +++++++++++++++++++
> >  1 file changed, 72 insertions(+)
> 
> I don't understand why this is a separate patch. It's not used, not
> effective and not visible for us how it extracts common parts.
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,

I completely misunderstood the suggestions given in V5, which led to
incorrect modifications and confusion in patches 2~5. I'm in the
process of rectifying these errors and respectfully ask everyone to
disregard the improper changes. I sincerely regret any inconvenience my
actions may have caused.

Regards,
Moudy
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-common.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-common.yaml
new file mode 100644
index 000000000000..8d2085f67d43
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma-common.yaml
@@ -0,0 +1,72 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Read Direct Memory Access
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+  - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+  MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
+  It contains one line buffer to store the sufficient pixel data, and
+  must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  reg:
+    maxItems: 1
+
+  mediatek,gce-client-reg:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle of GCE
+        - description: GCE subsys id
+        - description: register offset
+        - description: register size
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property. Each GCE subsys id is mapping to
+      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    maxItems: 1
+
+  mediatek,gce-events:
+    description:
+      The event id which is mapping to the specific hardware event signal
+      to gce. The event id is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 2
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  iommus:
+    maxItems: 1
+
+  mboxes:
+    minItems: 1
+    maxItems: 5
+
+  '#dma-cells':
+    const: 1
+
+required:
+  - reg
+  - mediatek,gce-client-reg
+  - power-domains
+  - clocks
+  - iommus
+  - '#dma-cells'
+
+additionalProperties: true