From patchwork Thu Dec 28 11:32:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 758708 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0065DDAF; Thu, 28 Dec 2023 11:33:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="1z0cOoyT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1703763182; bh=37Z5+7S5t846U9B0A0dcCmQr8H0ZxSimQ6IOeUd6EuQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1z0cOoyTvc9pTmCrf9DWg7bgLlojEZ8Oh50GKVtLwZuJPKIPvGJnhCnFjkoBTPWJ/ sAaRJD+I20+ohk1nhbTuxSymui4d5QhB8R/Xv5BDlYdpAonk8aIjMvuPRPTksXC3Jr yG57VuVD/NzJ5VfImR7Qd3lACDL6vcOWiUXO54E0j2wxbjRm17qgGeymzzo1mfmDdR N86OtiqbS1YkOa8ZVvvbb1YFpQK/l5VT0/DnTnjCwXcl5XQkuV5kP5qYSXp+9FEb5z 3xqCTQQZm/61IZDE+kRmbnf5fNsRNwkdKaHK1Gbj51XyTRfDdry/MRAZUMS1bFBS9g yp5c0wW841dmg== Received: from eugen-station.. (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: ehristev) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 3556C3781419; Thu, 28 Dec 2023 11:33:01 +0000 (UTC) From: Eugen Hristev To: tiffany.lin@mediatek.com, andrew-ct.chen@mediatek.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-mediatek@lists.infradead.org Cc: eugen.hristev@collabora.com, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, kernel@collabora.com, Kyrie Wu , Allen-KH Cheng , Hsin-Yi Wang Subject: [PATCH v3 6/6] arm64: dts: mediatek: mt8186: Add venc node Date: Thu, 28 Dec 2023 13:32:45 +0200 Message-Id: <20231228113245.174706-7-eugen.hristev@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231228113245.174706-1-eugen.hristev@collabora.com> References: <20231228113245.174706-1-eugen.hristev@collabora.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Kyrie Wu Add video encoder node. Signed-off-by: Kyrie Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Hsin-Yi Wang [eugen.hristev@collabora.com: minor cleanup] Signed-off-by: Eugen Hristev Reviewed-by: AngeloGioacchino Del Regno --- Changes in v3: - remove dma ranges and cells. Changes in v2: - change node name - change compatible to include 8186 - change props order - change clock name to cope with binding arch/arm64/boot/dts/mediatek/mt8186.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 66ead3f23336..bafb0845e986 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1993,6 +1993,27 @@ larb7: smi@17010000 { power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; }; + venc: video-encoder@17020000 { + compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>, + <&iommu_mm IOMMU_PORT_L7_VENC_REC>, + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>, + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>, + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>; + clocks = <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + mediatek,scp = <&scp>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8186-camsys"; reg = <0 0x1a000000 0 0x1000>;