From patchwork Mon Jun 24 12:13:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Chan via B4 Relay X-Patchwork-Id: 807136 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 646F013C90C; Mon, 24 Jun 2024 12:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719231236; cv=none; b=cVnF407lP977bYoWz+bs7rYvotv4FaGim+1r/nvs9+cUCpApSR+GV0ojVvp5mWJGod4SVqb/M4hDdMENZnUjsXB1DB+xRvYkKskuS58iEdUSiQG6IbTLJVEZKBS+48mLbHMCIoIII5a7P7H+BZetrG9+ZAAwkdxtmE0IKOeE9T0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719231236; c=relaxed/simple; bh=P7tRzXOzOr4abDBJLCa+Pyq0BwG37oH1SSrvN1JfE1E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oU4t7ZVE+08AG/+HRwN2YrPn+Jq8ZWCmAo2Iw5GUKHESvpax/aZ0bIg472wliFqlhCdyCZC2Abejtd/eHs7pgfq0GOkFSYW2OkYPBZa0+6Jk9wuHfSjZj42Ohzbonc6rsKJXP7jv+DjZGBgqmEsjwrV59vbPY5+pM9VnBHosQDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QKkB7jhY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QKkB7jhY" Received: by smtp.kernel.org (Postfix) with ESMTPS id AC4D3C4AF48; Mon, 24 Jun 2024 12:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719231235; bh=P7tRzXOzOr4abDBJLCa+Pyq0BwG37oH1SSrvN1JfE1E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QKkB7jhY3FKOq0p0I9OJ2q3Xcry/zlddwFepYHRsrH83OglHuZYSKvPO2GeCK8Yrv PTkh9JIFndyoHMvvx6wiz2A8QpK/LgfJAtGFqtRpZOes9GdjjxhVAX/z7dQ4HYDohF LcZlsvPHvD7b6aBI2Of8FIzyfHyuzGzYWv8DWwmavHfd2Q+rwwcvosY/58aHaJ6eNW PbWD65vDUtnHQcpjN7e7EmaA/k0XwfOp3o+/ANbM0wlek6bATGklsFVmerjqAByChT xyR0AJqoqLvCwa03k211v3rOIrtoS+Z2++WS29RSf91DdSZWvNjj0bEZgm88UfQ99r UnBaqONRAVtrw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 999E7C2D0D1; Mon, 24 Jun 2024 12:13:55 +0000 (UTC) From: George Chan via B4 Relay Date: Mon, 24 Jun 2024 20:13:16 +0800 Subject: [PATCH RFT v3 5/5] arm64: dts: qcom: sc7180: camss: Add CAMSS block definition Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-b4-sc7180-camss-v3-5-89ece6471431@gmail.com> References: <20240624-b4-sc7180-camss-v3-0-89ece6471431@gmail.com> In-Reply-To: <20240624-b4-sc7180-camss-v3-0-89ece6471431@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719231232; l=4398; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=on5h+5uBH0e6v/ZhEcYmVGb1x1th44JOiStLM0tExQM=; b=M2xosEuP+ZqXIojdE/P5QsEnKhYiVOP92VHbTCvN+9GkX9grEPsk8XDV82ep65frXHmQD4YbV gE5QotyKbYLCel5xh1sBzBnrpudO2JWXqIidphZ1XqtEnZ6YQ3oQnHR X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan Introduce camss subsys support to sc7180 family soc. Signed-off-by: George Chan Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 133 +++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b5ebf8980325..491c7981e23e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -3150,6 +3151,138 @@ camnoc_virt: interconnect@ac00000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + camss: camss@acb3000 { + compatible = "qcom,sc7180-camss"; + + reg = <0 0xacb3000 0 0x1000>, + <0 0xacba000 0 0x1000>, + <0 0xacc8000 0 0x1000>, + <0 0xac65000 0 0x1000>, + <0 0xac66000 0 0x1000>, + <0 0xac67000 0 0x1000>, + <0 0xac68000 0 0x1000>, + <0 0xacaf000 0 0x4000>, + <0 0xacb6000 0 0x4000>, + <0 0xacc4000 0 0x4000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + iommus = <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0x0>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names = "ife0", "ife1", "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc7180-camcc"; reg = <0 0x0ad00000 0 0x10000>;