From patchwork Thu Apr 17 06:55:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rishikesh Donadkar X-Patchwork-Id: 882515 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C295B21CA0D; Thu, 17 Apr 2025 06:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744873005; cv=none; b=iVLJfOG8PxKZd25468d/UoVIAjZFz38fOyh/cGtUYzvUmL2rea6UwBloBiM7CQMCTKuG+KVh9nCSsSFY1Rfzz9nTTt+k+hGdRkWUcaEBeyFqT5z32AHszyQ4ZtEY8mNQDNK4q4NhwBA+DxDZyiTOBjwLXKA9jwVf49v8iQvAt1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744873005; c=relaxed/simple; bh=zLUhmPReXzcz3gcRFoBawPQtidisRJ7ac5FF+ywNfhY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dB7iLkZ/SkeLsVeSJqn0v2M0KaXbqHAQjOFz6G8eDmKiJJN+GaDD8T7U0HWdnJH466QEC4A7AjQOsXU0EKxBn5srHuWSa+AMsPZnqR/c7mHuZowRbjMCB4cJgSMz7OuQ9rPsYxV6sMzFHjNh83dPEX2N4kXNa1WHfWfUmY95Rek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ilzvpnFC; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ilzvpnFC" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53H6uJwa564289 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Apr 2025 01:56:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744872979; bh=b/ravGOjy6gHVWbSnpREc7Wi0IqtPAjlLaNo0Crysgo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ilzvpnFCBJ6ROwxdfUKfBtt4LvW06+XR+uiqc3ynNokgd8Ziyx54JjxcFBRofQnT+ HV80KYuY6jqZRdb2VvrdDFQaAaxsPTAVTy8jOUMwGjSN04cBQpx5dT/iOGxZmmeLVC age+/BaX2fo/Ymorj+gN1gAcLW/Ew2znTWpeqnRg= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53H6uJxF032572 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Apr 2025 01:56:19 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 17 Apr 2025 01:56:18 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 17 Apr 2025 01:56:18 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [10.24.69.232]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53H6tsx3035403; Thu, 17 Apr 2025 01:56:13 -0500 From: Rishikesh Donadkar To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 03/13] media: ti: j721e-csi2rx: prepare SHIM code for multiple contexts Date: Thu, 17 Apr 2025 12:25:44 +0530 Message-ID: <20250417065554.437541-4-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250417065554.437541-1-r-donadkar@ti.com> References: <20250417065554.437541-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Pratyush Yadav Currently the SHIM code to configure the context only touches the first context. Add support for writing to the context's registers based on the context index. Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Reviewed-by: Jacopo Mondi Signed-off-by: Rishikesh Donadkar Reviewed-by: Laurent Pinchart --- .../media/platform/ti/j721e-csi2rx/j721e-csi2rx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 36cde2e87aabb..d03dc4e56d306 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -25,7 +25,7 @@ #define SHIM_CNTL 0x10 #define SHIM_CNTL_PIX_RST BIT(0) -#define SHIM_DMACNTX 0x20 +#define SHIM_DMACNTX(i) (0x20 + ((i) * 0x20)) #define SHIM_DMACNTX_EN BIT(31) #define SHIM_DMACNTX_YUV422 GENMASK(27, 26) #define SHIM_DMACNTX_SIZE GENMASK(21, 20) @@ -35,7 +35,7 @@ #define SHIM_DMACNTX_SIZE_16 1 #define SHIM_DMACNTX_SIZE_32 2 -#define SHIM_PSI_CFG0 0x24 +#define SHIM_PSI_CFG0(i) (0x24 + ((i) * 0x20)) #define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) #define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 16) @@ -549,11 +549,11 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx *ctx) reg |= FIELD_PREP(SHIM_DMACNTX_SIZE, fmt->size); - writel(reg, csi->shim + SHIM_DMACNTX); + writel(reg, csi->shim + SHIM_DMACNTX(ctx->idx)); reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) | FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 0); - writel(reg, csi->shim + SHIM_PSI_CFG0); + writel(reg, csi->shim + SHIM_PSI_CFG0(ctx->idx)); } static void ti_csi2rx_drain_callback(void *param) @@ -870,7 +870,7 @@ static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count) err_pipeline: video_device_pipeline_stop(&ctx->vdev); writel(0, csi->shim + SHIM_CNTL); - writel(0, csi->shim + SHIM_DMACNTX); + writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); err: ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_QUEUED); return ret; @@ -885,7 +885,7 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue *vq) video_device_pipeline_stop(&ctx->vdev); writel(0, csi->shim + SHIM_CNTL); - writel(0, csi->shim + SHIM_DMACNTX); + writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); ret = v4l2_subdev_call(csi->source, video, s_stream, 0); if (ret)