From patchwork Mon Dec 12 15:36:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 5602 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5375723E18 for ; Mon, 12 Dec 2011 15:36:44 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 412A1A18576 for ; Mon, 12 Dec 2011 15:36:44 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 17so7484197bke.11 for ; Mon, 12 Dec 2011 07:36:44 -0800 (PST) Received: by 10.204.157.12 with SMTP id z12mr7306487bkw.18.1323704204020; Mon, 12 Dec 2011 07:36:44 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs50802bkc; Mon, 12 Dec 2011 07:36:43 -0800 (PST) Received: by 10.213.3.150 with SMTP id 22mr1057520ebn.27.1323704202370; Mon, 12 Dec 2011 07:36:42 -0800 (PST) Received: from eu1sys200aog106.obsmtp.com (eu1sys200aog106.obsmtp.com. [207.126.144.121]) by mx.google.com with SMTP id h61si9568412eeh.140.2011.12.12.07.36.37 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 12 Dec 2011 07:36:42 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.121; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKTuYfgEt0cgBsj68HxLJLqLSD5heJsbZh@postini.com; Mon, 12 Dec 2011 15:36:41 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2EFE46F; Mon, 12 Dec 2011 15:28:01 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5368A10BE; Mon, 12 Dec 2011 15:36:27 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id C359024C2F3; Mon, 12 Dec 2011 16:36:18 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 12 Dec 2011 16:36:26 +0100 From: Ulf Hansson To: , Cc: Russell King , Ulf Hansson , Lee Jones , Per Forlin , Stefan Nilsson XK Subject: [PATCH 3/5] mmc: mmci: Add constraints on alignment for SDIO Date: Mon, 12 Dec 2011 16:36:05 +0100 Message-ID: <1323704167-10247-4-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323704167-10247-1-git-send-email-ulf.hansson@stericsson.com> References: <1323704167-10247-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 From: Per Forlin Buffers must be 4-byte aligned due to restrictions that the PL18x FIFO accesses must be done in a 4-byte aligned manner. Moreover DPSM_DMAREQCTL must be enabled for SDIO to support writes for non 32-byte aligned sg element lengths. In PIO mode any buffer length can be handled as long as the buffer address is 4-byte aligned. Signed-off-by: Ulf Hansson Signed-off-by: Per Forlin Signed-off-by: Stefan Nilsson XK --- drivers/mmc/host/mmci.c | 51 +++++++++++++++++++++++++++++++++++++++++----- drivers/mmc/host/mmci.h | 7 ++++++ 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index b949e07..9ea2f13 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -45,6 +45,7 @@ static unsigned int fmax = 515633; * struct variant_data - MMCI variant-specific quirks * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register + * @dma_sdio_req_ctrl: enable value for DMAREQCTL register for SDIO write * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -60,6 +61,7 @@ static unsigned int fmax = 515633; struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; + unsigned int dma_sdio_req_ctrl; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -102,6 +104,7 @@ static struct variant_data variant_ux500 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .dma_sdio_req_ctrl = MCI_ST_DPSM_DMAREQCTL, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, @@ -114,6 +117,7 @@ static struct variant_data variant_ux500v2 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .dma_sdio_req_ctrl = MCI_ST_DPSM_DMAREQCTL, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, @@ -123,6 +127,30 @@ static struct variant_data variant_ux500v2 = { }; /* + * Validate mmc prerequisites + */ +static int mmci_validate_data(struct mmci_host *host, + struct mmc_data *data) +{ + if (!data) + return 0; + + if (!is_power_of_2(data->blksz)) { + dev_err(mmc_dev(host->mmc), + "unsupported block size (%d bytes)\n", data->blksz); + return -EINVAL; + } + + if (data->sg->offset & 3) { + dev_err(mmc_dev(host->mmc), + "unsupported alignment (0x%x)\n", data->sg->offset); + return -EINVAL; + } + + return 0; +} + +/* * This must be called with host->lock held */ static void mmci_write_clkreg(struct mmci_host *host, u32 clk) @@ -432,8 +460,12 @@ static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, if (!chan) return -EINVAL; - /* If less than or equal to the fifo size, don't bother with DMA */ - if (data->blksz * data->blocks <= variant->fifosize) + /* + * If less than or equal to the fifo size, don't bother with DMA. + * SDIO transfers may not be 4-byte aligned, fall back to PIO. + */ + if (data->blksz * data->blocks <= variant->fifosize || + (data->blksz * data->blocks) & 3) return -EINVAL; device = chan->device; @@ -468,6 +500,7 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) { int ret; struct mmc_data *data = host->data; + struct variant_data *variant = host->variant; ret = mmci_dma_prep_data(host, host->data, NULL); if (ret) @@ -482,6 +515,11 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) datactrl |= MCI_DPSM_DMAENABLE; + /* Some hardware versions need special flags for SDIO DMA write. */ + if (variant->sdio && host->mmc->card && mmc_card_sdio(host->mmc->card) + && (data->flags & MMC_DATA_WRITE)) + datactrl |= variant->dma_sdio_req_ctrl; + /* Trigger the DMA transfer */ writel(datactrl, host->base + MMCIDATACTRL); @@ -526,6 +564,9 @@ static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, if (!data) return; + if (mmci_validate_data(host, mrq->data)) + return; + if (data->host_cookie) { data->host_cookie = 0; return; @@ -1019,10 +1060,8 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) WARN_ON(host->mrq != NULL); - if (mrq->data && !is_power_of_2(mrq->data->blksz)) { - dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", - mrq->data->blksz); - mrq->cmd->error = -EINVAL; + mrq->cmd->error = mmci_validate_data(host, mrq->data); + if (mrq->cmd->error) { mmc_request_done(mmc, mrq); return; } diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index d437ccf..095c01c 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -60,6 +60,13 @@ #define MCI_ST_DPSM_RWMOD (1 << 10) #define MCI_ST_DPSM_SDIOEN (1 << 11) /* Control register extensions in the ST Micro Ux500 versions */ +/* + * DMA request control is required for write + * if transfer size is not 32-byte aligned. + * DMA request control is also needed if the total + * transfer size is 32-byte aligned but any of the + * sg element lengths are not 32-byte aligned. + */ #define MCI_ST_DPSM_DMAREQCTL (1 << 12) #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) #define MCI_ST_DPSM_BUSYMODE (1 << 14)